X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=3abcd68d29a9c0f813ef06c3a3391b7c4dc58c1f;hb=b03e2209d5e83e3c1b9737097b13109c7e4658c3;hp=8579258d33d70de95ebc90c1e296cd035d6e33a5;hpb=486b19ce017c6663be6574dacd0c823304903bca;p=libsigrokdecode.git

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 8579258..3abcd68 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -35,9 +35,12 @@ Packet:
  - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
    item, and for each of those also their respective start-/endsample numbers.
  - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
-   Both data items are Python numbers (0/1), not strings.
+   Both data items are Python numbers (0/1), not strings. At the beginning of
+   the decoding a packet is generated with <data1> = None and <data2> being the
+   initial state of the CS# pin or None if the chip select pin is not supplied.
 
 Examples:
+ ['CS-CHANGE', None, 1]
  ['CS-CHANGE', 1, 0]
  ['DATA', 0xff, 0x3a]
  ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
@@ -108,6 +111,10 @@ class Decoder(srd.Decoder):
         ('mosi-bits', 'MOSI bits', (3,)),
         ('other', 'Other', (4,)),
     )
+    binary = (
+        ('miso', 'MISO'),
+        ('mosi', 'MOSI'),
+    )
 
     def __init__(self):
         self.samplerate = None
@@ -119,9 +126,10 @@ class Decoder(srd.Decoder):
         self.ss_block = -1
         self.samplenum = -1
         self.cs_was_deasserted = False
-        self.oldcs = -1
+        self.oldcs = None
         self.oldpins = None
         self.have_cs = self.have_miso = self.have_mosi = None
+        self.no_cs_notification = False
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
@@ -130,6 +138,7 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_bin = self.register(srd.OUTPUT_BINARY)
         self.out_bitrate = self.register(srd.OUTPUT_META,
                 meta=(int, 'Bitrate', 'Bitrate during transfers'))
 
@@ -145,8 +154,10 @@ class Decoder(srd.Decoder):
 
         if self.have_miso:
             ss, es = self.misobits[-1][1], self.misobits[0][2]
+            self.put(ss, es, self.out_bin, (0, bytes([so])))
         if self.have_mosi:
             ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+            self.put(ss, es, self.out_bin, (1, bytes([si])))
 
         self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
         self.put(ss, es, self.out_python, ['DATA', si, so])
@@ -281,4 +292,9 @@ class Decoder(srd.Decoder):
             if not (self.have_miso or self.have_mosi):
                 raise ChannelError('Either MISO or MOSI (or both) pins required.')
 
+            # Tell stacked decoders that we don't have a CS# signal.
+            if not self.no_cs_notification and not self.have_cs:
+                self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
+                self.no_cs_notification = True
+
             self.find_clk_edge(miso, mosi, clk, cs)