X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fsignature%2Fpd.py;h=946b2da7574e7fb4b01e0caeb0d584fa1dee1ff5;hb=0963cf62de26f00f2cbfcd2b4a841bf0a9c05384;hp=797a004521c846ba9a6fdd1c9d9a05faa5a67b31;hpb=201ad73b706f6beaef0d782bbf3c353073442d8d;p=libsigrokdecode.git

diff --git a/decoders/signature/pd.py b/decoders/signature/pd.py
index 797a004..946b2da 100644
--- a/decoders/signature/pd.py
+++ b/decoders/signature/pd.py
@@ -46,7 +46,7 @@ class Decoder(srd.Decoder):
     name = 'Signature'
     longname = 'Signature analysis'
     desc = 'Annotate signature of logic patterns.'
-    license = 'gplv3+'
+    license = 'gplv2+'
     inputs = ['logic']
     outputs = []
     tags = ['Debug/trace', 'Util', 'Encoding']
@@ -58,11 +58,11 @@ class Decoder(srd.Decoder):
     )
     options = (
         {'id': 'start_edge', 'desc': 'START edge polarity',
-            'default': 'r', 'values': ('r', 'f')},
+            'default': 'rising', 'values': ('rising', 'falling')},
         {'id': 'stop_edge', 'desc': 'STOP edge polarity',
-            'default': 'r', 'values': ('r', 'f')},
+            'default': 'rising', 'values': ('rising', 'falling')},
         {'id': 'clk_edge', 'desc': 'CLOCK edge polarity',
-            'default': 'f', 'values': ('r', 'f')},
+            'default': 'falling', 'values': ('rising', 'falling')},
         {'id': 'annbits', 'desc': 'Enable bit level annotations',
             'default': 'no', 'values': ('yes', 'no')},
     )
@@ -71,11 +71,11 @@ class Decoder(srd.Decoder):
         ('bit1', 'Bit1'),
         ('start', 'START'),
         ('stop', 'STOP'),
-        ('sig', 'Sig')
+        ('signature', 'Signature')
     )
     annotation_rows = (
         ('bits', 'Bits', (0, 1, 2, 3)),
-        ('sig', 'Sig', (4,))
+        ('signatures', 'Signatures', (4,))
     )
 
     def __init__(self):
@@ -99,8 +99,8 @@ class Decoder(srd.Decoder):
 
     def decode(self):
         opt = self.options
-        start_edge_mode_rising = opt['start_edge'] == 'r'
-        stop_edge_mode_rising = opt['stop_edge'] == 'r'
+        start_edge_mode_rising = opt['start_edge'] == 'rising'
+        stop_edge_mode_rising = opt['stop_edge'] == 'rising'
         annbits = opt['annbits'] == 'yes'
         gate_is_open = False
         sample_start = None
@@ -135,7 +135,7 @@ class Decoder(srd.Decoder):
                         started = False
                     else:
                         self.putb(last_samplenum, [data, [str(data)]])
-                incoming = (bin(shiftreg & 0b0000_0010_1001_0001).count('1') + data) & 1
+                incoming = (bin(shiftreg & 0x0291).count('1') + data) & 1
                 shiftreg = (incoming << 15) | (shiftreg >> 1)
             prev_start = start
             prev_stop = stop