X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Frtc8564%2Fpd.py;h=f13af364fe14dd731c639667ac7419989dc0c339;hb=12851357e784b893e24880efc6cd22a0cbcc64ce;hp=8a2fbf9592abb7a5597d8eb8f762a8e6096cb6af;hpb=ae33d639670cd4ca6bfe683c4284dd55377e5f21;p=libsigrokdecode.git

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index 8a2fbf9..f13af36 100644
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -24,8 +24,15 @@ import sigrokdecode as srd
 def bcd2int(b):
     return (b & 0x0f) + ((b >> 4) * 10)
 
+def reg_list():
+    l = []
+    for i in range(8 + 1):
+        l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))
+
+    return tuple(l)
+
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'rtc8564'
     name = 'RTC-8564'
     longname = 'Epson RTC-8564 JE/NB'
@@ -33,23 +40,15 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['i2c']
     outputs = ['rtc8564']
-    probes = []
-    optional_probes = [
-        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
-        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
-        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
-    ]
-    options = {}
-    annotations = \
-        [['reg-0x%02x' % i, 'Register 0x%02x' % i] for i in range(8 + 1)] + [
-        ['read', 'Read date/time'],
-        ['write', 'Write date/time'],
-        ['bit-reserved', 'Reserved bit'],
-        ['bit-vl', 'VL bit'],
-        ['bit-century', 'Century bit'],
-        ['reg-read', 'Register read'],
-        ['reg-write', 'Register write'],
-    ]
+    annotations = reg_list() + (
+        ('read', 'Read date/time'),
+        ('write', 'Write date/time'),
+        ('bit-reserved', 'Reserved bit'),
+        ('bit-vl', 'VL bit'),
+        ('bit-century', 'Century bit'),
+        ('reg-read', 'Register read'),
+        ('reg-write', 'Register write'),
+    )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
         ('regs', 'Register access', (14, 15)),
@@ -68,7 +67,6 @@ class Decoder(srd.Decoder):
         self.bits = []
 
     def start(self):
-        # self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putx(self, data):