X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fpjdl%2Fpd.py;h=d5cc39f22ba37c36eb1657843595c19f9b433195;hb=f9818294d09ba8b7dd3614357ce185f79c8c45a1;hp=2d4fb0da2fd9a38505849c62d8bf13e3ff762adc;hpb=db18ba49bcbe38a9a67297207d821bf0e1e9dc4c;p=libsigrokdecode.git

diff --git a/decoders/pjdl/pd.py b/decoders/pjdl/pd.py
index 2d4fb0d..d5cc39f 100644
--- a/decoders/pjdl/pd.py
+++ b/decoders/pjdl/pd.py
@@ -119,8 +119,8 @@ class Decoder(srd.Decoder):
     desc = 'PJDL, a single wire serial link layer for PJON.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['pjon-link']
-    tags = ['Embedded']
+    outputs = ['pjon_link']
+    tags = ['Embedded/industrial']
     channels = (
         {'id': 'data' , 'name': 'DATA', 'desc': 'Single wire data'},
     )
@@ -387,7 +387,9 @@ class Decoder(srd.Decoder):
         # for bit widths (tolerance margin).
 
         # Get times in microseconds.
-        self.data_width, self.pad_width = self.mode_times[self.options['mode']]
+        mode_times = self.mode_times[self.options['mode']]
+        mode_times = [t * 1.0 for t in mode_times]
+        self.data_width, self.pad_width = mode_times
         self.byte_width = self.pad_width + 9 * self.data_width
         self.add_idle_width = self.options['idle_add_us']
         self.idle_width = self.byte_width + self.add_idle_width
@@ -508,7 +510,9 @@ class Decoder(srd.Decoder):
             is_short = bit_level and self.span_is_short(span)
 
             if is_pad:
-                ss, es = last_snum, curr_snum
+                # BEWARE! Use ss value of last edge (genuinely seen, or
+                # inserted after a DATA byte) for PAD bit annotations.
+                ss, es = self.edges[-2], curr_snum
                 texts = ['PAD', '{:d}'.format(bit_level)]
                 self.putg(ss, es, [ANN_PAD_BIT, texts])
                 self.symbols_append(ss, es, 'PAD_BIT', bit_level)
@@ -672,10 +676,20 @@ class Decoder(srd.Decoder):
             # the transmitter's and the sender's timings differ within a
             # margin, and the transmitter may hold the last DATA bit's
             # HIGH level for a little longer.
+            #
+            # When no falling edge is seen within the maximum tolerance
+            # for the last DATA bit, then this could be the combination
+            # of a HIGH DATA bit and a PAD bit without a LOW in between.
+            # Fake an edge in that case, to re-use existing code paths.
+            # Make sure to keep referencing times to the last SYNC pad's
+            # falling edge. This is the last reliable condition we have.
             if curr_level:
                 hold = self.hold_high_width
                 curr_level, = self.wait([{PIN_DATA: 'l'}, {'skip': int(hold)}])
                 self.carrier_check(curr_level, self.samplenum)
+                if self.matched[1]:
+                    self.edges.append(curr_snum)
+                    curr_level = 1 - curr_level
                 curr_snum = self.samplenum
 
             # Get the byte value from the bits (when available).