X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fpca9571%2Fpd.py;h=ea8715d6d2ca15c1fecfd5d7b61ddc18a9eae215;hb=de219b2b77dba06815869823789458581500ca03;hp=af0ad2d1763f253d4627a10616549a50bd1e149d;hpb=9b6c0354ce4bab15c524928f2c0059f1df543ad9;p=libsigrokdecode.git diff --git a/decoders/pca9571/pd.py b/decoders/pca9571/pd.py index af0ad2d..ea8715d 100644 --- a/decoders/pca9571/pd.py +++ b/decoders/pca9571/pd.py @@ -56,24 +56,23 @@ class Decoder(srd.Decoder): def reset(self): self.state = 'IDLE' self.last_write = 0xFF # Chip port default state is high. - - self.logic_es = 1 - self.logic_data = [] - for i in range(NUM_OUTPUT_CHANNELS): - self.logic_data.append(bytes([1])) + self.last_write_es = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) self.out_logic = self.register(srd.OUTPUT_LOGIC) + def flush(self): + self.put_logic_states() + def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) def put_logic_states(self): - if (self.es > self.logic_es): - for i in range(NUM_OUTPUT_CHANNELS): - self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) - self.logic_es = self.es + if (self.es > self.last_write_es): + data = bytes([self.last_write]) + self.put(self.last_write_es, self.es, self.out_logic, [0, data]) + self.last_write_es = self.es def handle_io(self, b): if self.state == 'READ DATA': @@ -83,14 +82,12 @@ class Decoder(srd.Decoder): '(%02X) are different' % self.last_write]]) else: operation = ['Outputs set', 'W'] + self.put_logic_states() self.last_write = b + self.putx([1, [operation[0] + ': %02X' % b, operation[1] + ': %02X' % b]]) - for i in range(NUM_OUTPUT_CHANNELS): - bit = (b & (1 << i)) != 0 - self.logic_data[i] = bytes([bit]) - def check_correct_chip(self, addr): if addr != 0x25: self.putx([2, ['Warning: I²C slave 0x%02X not a PCA9571 ' @@ -102,8 +99,6 @@ class Decoder(srd.Decoder): cmd, databyte = data self.ss, self.es = ss, es - self.put_logic_states() - # State machine. if cmd in ('ACK', 'BITS'): # Discard 'ACK' and 'BITS'. pass