X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=cafaefc071b4904718c84ab5e589bb695d005ea5;hb=e4227bafd63472d1a0d23fa54f62a2b20e296115;hp=cae269f8d524c5bf403164f8ac0e048ee28edf34;hpb=da9bcbd9f45b0153465c55ec726a0d76f6d7f01e;p=libsigrokdecode.git diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py index cae269f..cafaefc 100644 --- a/decoders/parallel/pd.py +++ b/decoders/parallel/pd.py @@ -54,15 +54,18 @@ Packet: word is 7, and so on. ''' -def probe_list(num_probes): +def channel_list(num_channels): l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}] - for i in range(num_probes): + for i in range(num_channels): d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i} l.append(d) return tuple(l) +class ChannelError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'parallel' name = 'Parallel' longname = 'Parallel sync bus' @@ -70,13 +73,12 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['parallel'] - optional_probes = probe_list(8) + optional_channels = channel_list(8) options = ( {'id': 'clock_edge', 'desc': 'Clock edge to sample on', 'default': 'rising', 'values': ('rising', 'falling')}, - {'id': 'wordsize', 'desc': 'Word size of the data', - 'default': 1}, - {'id': 'endianness', 'desc': 'Endianness of the data', + {'id': 'wordsize', 'desc': 'Data wordsize', 'default': 1}, + {'id': 'endianness', 'desc': 'Data endianness', 'default': 'little', 'values': ('little', 'big')}, ) annotations = ( @@ -93,7 +95,6 @@ class Decoder(srd.Decoder): self.oldpins = None self.ss_item = self.es_item = None self.first = True - self.state = 'IDLE' def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -124,7 +125,7 @@ class Decoder(srd.Decoder): self.items.append(item) self.itemcount += 1 - if self.first == True: + if self.first: # Save the start sample and item for later (no output yet). self.ss_item = self.samplenum self.first = False @@ -182,12 +183,10 @@ class Decoder(srd.Decoder): continue self.oldpins = pins - # State machine. - if self.state == 'IDLE': - if pins[0] not in (0, 1): - self.handle_bits(pins[1:]) - else: - self.find_clk_edge(pins[0], pins[1:]) - else: - raise Exception('Invalid state: %s' % self.state) + if sum(1 for p in pins if p in (0, 1)) == 0: + raise ChannelError('At least one channel has to be supplied.') + if pins[0] not in (0, 1): + self.handle_bits(pins[1:]) + else: + self.find_clk_edge(pins[0], pins[1:])