X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=b2903d20e4b41425a4edc2163d990f095d1ee0e8;hb=361c1e76a85bb14dce7b9f3e97deb9fe09416a7b;hp=9c203543f21a65593df2eea5b753dc1a1c32b6f4;hpb=be465111b552c7c2a2262ac49758a30a8bf1b1d5;p=libsigrokdecode.git

diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index 9c20354..b2903d2 100644
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -18,12 +18,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# Parallel (sync) bus protocol decoder
-
 import sigrokdecode as srd
 
 '''
-Protocol output format:
+OUTPUT_PYTHON format:
 
 Packet:
 [<ptype>, <pdata>]
@@ -57,7 +55,7 @@ Packet:
 '''
 
 def probe_list(num_probes):
-    l = []
+    l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
     for i in range(num_probes):
         d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
         l.append(d)
@@ -72,9 +70,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['parallel']
-    probes = [
-        {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
-    ]
+    probes = []
     optional_probes = probe_list(8)
     options = {
         'clock_edge': ['Clock edge to sample on', 'rising'],
@@ -98,21 +94,18 @@ class Decoder(srd.Decoder):
         self.first = True
         self.state = 'IDLE'
 
-    def start(self, metadata):
-        self.out_proto = self.register(srd.OUTPUT_PYTHON)
+    def start(self):
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
-    def report(self):
-        pass
-
     def putpb(self, data):
-        self.put(self.ss_item, self.es_item, self.out_proto, data)
+        self.put(self.ss_item, self.es_item, self.out_python, data)
 
     def putb(self, data):
         self.put(self.ss_item, self.es_item, self.out_ann, data)
 
     def putpw(self, data):
-        self.put(self.ss_word, self.es_word, self.out_proto, data)
+        self.put(self.ss_word, self.es_word, self.out_python, data)
 
     def putw(self, data):
         self.put(self.ss_word, self.es_word, self.out_ann, data)
@@ -149,7 +142,7 @@ class Decoder(srd.Decoder):
         if self.itemcount < ws:
             return
 
-        # Output annotations/proto for a word (a collection of items).
+        # Output annotations/python for a word (a collection of items).
         word = 0
         for i in range(ws):
             if endian == 'little':
@@ -190,7 +183,10 @@ class Decoder(srd.Decoder):
 
             # State machine.
             if self.state == 'IDLE':
-                self.find_clk_edge(pins[0], pins[1:])
+                if pins[0] not in (0, 1):
+                    self.handle_bits(pins[1:])
+                else:
+                    self.find_clk_edge(pins[0], pins[1:])
             else:
                 raise Exception('Invalid state: %s' % self.state)