X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=1c3435c23943d6a6f702dbd56a97987a894f7ecf;hb=a0b7e07f5576605141e543f9d81a220a920edc27;hp=cafaefc071b4904718c84ab5e589bb695d005ea5;hpb=a573d3944c410d90adb5130323e0f3792d9ae201;p=libsigrokdecode.git diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py index cafaefc..1c3435c 100644 --- a/decoders/parallel/pd.py +++ b/decoders/parallel/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2013 Uwe Hermann +## Copyright (C) 2013-2016 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,11 +14,11 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd +from common.srdhelper import bitpack ''' OUTPUT_PYTHON format: @@ -64,8 +64,10 @@ def channel_list(num_channels): class ChannelError(Exception): pass +NUM_CHANNELS = 8 + class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'parallel' name = 'Parallel' longname = 'Parallel sync bus' @@ -73,7 +75,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['parallel'] - optional_channels = channel_list(8) + optional_channels = channel_list(NUM_CHANNELS) options = ( {'id': 'clock_edge', 'desc': 'Clock edge to sample on', 'default': 'rising', 'values': ('rising', 'falling')}, @@ -87,12 +89,11 @@ class Decoder(srd.Decoder): ) def __init__(self): - self.oldclk = None + self.reset() + + def reset(self): self.items = [] - self.itemcount = 0 self.saved_item = None - self.samplenum = 0 - self.oldpins = None self.ss_item = self.es_item = None self.first = True @@ -112,18 +113,11 @@ class Decoder(srd.Decoder): def putw(self, data): self.put(self.ss_word, self.es_word, self.out_ann, data) - def handle_bits(self, datapins): - # If this is the first item in a word, save its sample number. - if self.itemcount == 0: + def handle_bits(self, item, used_pins): + # Save the item, and its sample number if it's the first part of a word. + if not self.items: self.ss_word = self.samplenum - - # Get the bits for this item. - item, used_pins = 0, datapins.count(b'\x01') + datapins.count(b'\x00') - for i in range(used_pins): - item |= datapins[i] << i - self.items.append(item) - self.itemcount += 1 if self.first: # Save the start sample and item for later (no output yet). @@ -138,55 +132,58 @@ class Decoder(srd.Decoder): self.ss_item = self.samplenum self.saved_item = item - endian, ws = self.options['endianness'], self.options['wordsize'] - # Get as many items as the configured wordsize says. - if self.itemcount < ws: + ws = self.options['wordsize'] + if len(self.items) < ws: return # Output annotations/python for a word (a collection of items). + # NOTE that this feature is currently not effective. The emission + # of Python annotations is commented out. + endian = self.options['endianness'] + if endian == 'little': + self.items.reverse() word = 0 for i in range(ws): - if endian == 'little': - word |= self.items[i] << ((ws - 1 - i) * used_pins) - elif endian == 'big': - word |= self.items[i] << (i * used_pins) + word |= self.items[i] << (i * used_pins) self.es_word = self.samplenum # self.putpw(['WORD', word]) # self.putw([1, ['%X' % word]]) self.ss_word = self.samplenum - self.itemcount, self.items = 0, [] - - def find_clk_edge(self, clk, datapins): - # Ignore sample if the clock pin hasn't changed. - if clk == self.oldclk: - return - self.oldclk = clk - - # Sample data on rising/falling clock edge (depends on config). - c = self.options['clock_edge'] - if c == 'rising' and clk == 0: # Sample on rising clock edge. - return - elif c == 'falling' and clk == 1: # Sample on falling clock edge. - return - - # Found the correct clock edge, now get the bits. - self.handle_bits(datapins) - - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins = pins - - if sum(1 for p in pins if p in (0, 1)) == 0: - raise ChannelError('At least one channel has to be supplied.') + self.items = [] - if pins[0] not in (0, 1): - self.handle_bits(pins[1:]) - else: - self.find_clk_edge(pins[0], pins[1:]) + def decode(self): + # Determine which (optional) channels have input data. Insist in + # a non-empty input data set. Cope with sparse connection maps. + # Store enough state to later "compress" sampled input data. + max_possible = len(self.optional_channels) + idx_channels = [ + idx if self.has_channel(idx) else None + for idx in range(max_possible) + ] + has_channels = [idx for idx in idx_channels if idx is not None] + if not has_channels: + raise ChannelError('At least one channel has to be supplied.') + max_connected = max(has_channels) + idx_strip = max_connected + 1 + + # Determine .wait() conditions, depending on the presence of a + # clock signal. Either inspect samples on the configured edge of + # the clock, or inspect samples upon ANY edge of ANY of the pins + # which provide input data. + if self.has_channel(0): + edge = self.options['clock_edge'][0] + conds = {0: edge} + else: + conds = [{idx: 'e'} for idx in has_channels] + + # Keep processing the input stream. Assume "always zero" for + # not-connected input lines. Pass data bits (all inputs except + # clock) to the handle_bits() method. + while True: + pins = self.wait(conds) + bits = [0 if idx is None else pins[idx] for idx in idx_channels] + bits = bits[1:idx_strip] + self.handle_bits(bitpack(bits), len(bits))