X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fnrf905%2Fpd.py;h=12949fea618c1d8dc5d0b42f43b0e5e90cb9b88e;hb=HEAD;hp=076fbeddd8478a27174c8ec0b13268dfc87a4f4e;hpb=826981ac5a2105c7231aeb5e5e523cd37ce72edd;p=libsigrokdecode.git diff --git a/decoders/nrf905/pd.py b/decoders/nrf905/pd.py index 076fbed..12949fe 100644 --- a/decoders/nrf905/pd.py +++ b/decoders/nrf905/pd.py @@ -22,6 +22,7 @@ ## SOFTWARE. import sigrokdecode as srd +from common.srdhelper import SrdIntEnum CFG_REGS = { 0: [{'name': 'CH_NO', 'stbit': 7, 'nbits': 8}], @@ -74,6 +75,8 @@ STAT_REG = [ {'name': 'DR', 'stbit': 5, 'nbits': 1}, ] +Ann = SrdIntEnum.from_str('Ann', 'CMD REG_WR REG_RD TX RX RESP WARN') + class Decoder(srd.Decoder): api_version = 3 id = 'nrf905' @@ -82,8 +85,8 @@ class Decoder(srd.Decoder): desc = '433/868/933MHz transceiver chip.' license = 'mit' inputs = ['spi'] - outputs = ['nrf905'] - + outputs = [] + tags = ['IC', 'Wireless/RF'] annotations = ( ('cmd', 'Command sent to the device'), ('reg-write', 'Config register written to the device'), @@ -91,24 +94,15 @@ class Decoder(srd.Decoder): ('tx-data', 'Payload sent to the device'), ('rx-data', 'Payload read from the device'), ('resp', 'Response to commands received from the device'), - ('warning', 'Warning') + ('warning', 'Warning'), ) - - ann_cmd = 0 - ann_reg_wr = 1 - ann_reg_rd = 2 - ann_tx = 3 - ann_rx = 4 - ann_resp = 5 - ann_warn = 6 - annotation_rows = ( - ('commands', 'Commands', (ann_cmd,)), - ('responses', 'Responses', (ann_resp,)), - ('registers', 'Registers', (ann_reg_wr, ann_reg_rd)), - ('tx', 'Transmitted data', (ann_tx,)), - ('rx', 'Received data', (ann_rx,)), - ('warnings', 'Warnings', (ann_warn,)) + ('commands', 'Commands', (Ann.CMD,)), + ('responses', 'Responses', (Ann.RESP,)), + ('registers', 'Registers', (Ann.REG_WR, Ann.REG_RD)), + ('tx', 'Transmitted data', (Ann.TX,)), + ('rx', 'Received data', (Ann.RX,)), + ('warnings', 'Warnings', (Ann.WARN,)), ) def __init__(self): @@ -126,10 +120,8 @@ class Decoder(srd.Decoder): def extract_bits(self, byte, start_bit, num_bits): begin = 7 - start_bit end = begin + num_bits - if begin < 0 or end > 8: return 0 - binary = format(byte, '08b')[begin:end] return int(binary, 2) @@ -137,22 +129,18 @@ class Decoder(srd.Decoder): # Iterate all vars on current register. data = '' for var in reg_vars: - var_value = self.extract_bits(reg_value, var['stbit'], - var['nbits']) + var_value = self.extract_bits(reg_value, var['stbit'], var['nbits']) data += var['name'] + ' = ' + str(var_value) opt = '' # If var has options, just add the option meaning. if 'opts' in var: - if var_value in var['opts']: - opt = var['opts'][var_value] - else: - opt = 'unknown' + opt = var['opts'].get(var_value, 'unknown') data += ' (' + opt + ')' # Add var separator. if reg_vars.index(var) != len(reg_vars) - 1: - data = data + ' | ' + data += ' | ' return data def parse_config_register(self, addr, value, is_write): @@ -165,16 +153,12 @@ class Decoder(srd.Decoder): else: # Invalid register address. self.put(value[1], value[2], - self.out_ann, [self.ann_warn, ['Invalid reg. addr']]) + self.out_ann, [Ann.WARN, ['Invalid reg. addr']]) return data += self.extract_vars(reg_vars, reg_value) - if is_write: - ann = self.ann_reg_wr - else: - ann = self.ann_reg_rd - + ann = Ann.REG_WR if is_write else Ann.REG_RD self.put(value[1], value[2], self.out_ann, [ann, [data]]) def parse_config_registers(self, addr, registers, is_write): @@ -183,79 +167,58 @@ class Decoder(srd.Decoder): reg_addr = i + addr if reg_addr <= 9: self.parse_config_register(reg_addr, registers[i], is_write) - else: - print('INVALID REGISTER ADDR ' + hex(reg_addr)) i += 1 def dump_cmd_bytes(self, prefix, cmd_bytes, ann): - ss = cmd_bytes[1][1] - es = 0 + ss, es = cmd_bytes[1][1], 0 data = '' for byte in cmd_bytes[1:]: - data += '0x' + format(byte[0], '02x') + ' ' + data += format(byte[0], '02X') + ' ' es = byte[2] - self.put(ss, es, self.out_ann, [ann, [prefix + data]]) def handle_WC(self): start_addr = self.mosi_bytes[0][0] & 0x0F - if start_addr > 9: - print('ERROR: WRONG OFFSET') return - self.parse_config_registers(start_addr, self.mosi_bytes[1:], True) def handle_RC(self): start_addr = self.mosi_bytes[0][0] & 0x0F - if start_addr > 9: - print('ERROR: WRONG OFFSET') return self.parse_config_registers(start_addr, self.miso_bytes[1:], False) def handle_WTP(self): - self.dump_cmd_bytes('Write TX payload.: ', - self.mosi_bytes, self.ann_tx) + self.dump_cmd_bytes('Write TX payload.: ', self.mosi_bytes, Ann.TX) def handle_RTP(self): - self.dump_cmd_bytes('Read TX payload: ', - self.miso_bytes, self.ann_resp) + self.dump_cmd_bytes('Read TX payload: ', self.miso_bytes, Ann.RESP) def handle_WTA(self): - self.dump_cmd_bytes('Write TX addr: ', - self.mosi_bytes, self.ann_reg_wr) + self.dump_cmd_bytes('Write TX addr: ', self.mosi_bytes, Ann.REG_WR) def handle_RTA(self): - self.dump_cmd_bytes('Read TX addr: ', - self.miso_bytes, self.ann_resp) + self.dump_cmd_bytes('Read TX addr: ', self.miso_bytes, Ann.RESP) def handle_RRP(self): - self.dump_cmd_bytes('Read RX payload: ', - self.miso_bytes, self.ann_rx) + self.dump_cmd_bytes('Read RX payload: ', self.miso_bytes, Ann.RX) def handle_CC(self): - cmd = self.mosi_bytes[0] - dta = self.mosi_bytes[1] - - channel = (cmd[0] & 0x01) << 8 - channel = channel + dta[0] - + cmd, dta = self.mosi_bytes[0], self.mosi_bytes[1] + channel = ((cmd[0] & 0x01) << 8) + dta data = self.extract_vars(CHN_CFG, cmd[0]) - - data = data + '| CHN = ' + str(channel) + data += '| CHN = ' + str(channel) self.put(self.mosi_bytes[0][1], self.mosi_bytes[1][2], - self.out_ann, [self.ann_reg_wr, [data]]) + self.out_ann, [Ann.REG_WR, [data]]) def handle_STAT(self): status = 'STAT = ' + self.extract_vars(STAT_REG, self.miso_bytes[0][0]) self.put(self.miso_bytes[0][1], self.miso_bytes[0][2], - self.out_ann, [self.ann_reg_rd, [status]]) + self.out_ann, [Ann.REG_RD, [status]]) def process_cmd(self): - cmd = '' - cmd_name = '' - cmd_hnd = None + cmd, cmd_name, cmd_hnd = '', '', None for byte in self.mosi_bytes: cmd += hex(byte[0]) + ' ' @@ -263,40 +226,25 @@ class Decoder(srd.Decoder): cmd = self.mosi_bytes[0][0] if (cmd & 0xF0) == 0x00: - cmd_name = 'CMD: W_CONFIG (WC)' - cmd_hnd = self.handle_WC - + cmd_name, cmd_hnd = 'CMD: W_CONFIG (WC)', self.handle_WC elif (cmd & 0xF0) == 0x10: - cmd_name = 'CMD: R_CONFIG (RC)' - cmd_hnd = self.handle_RC - + cmd_name, cmd_hnd = 'CMD: R_CONFIG (RC)', self.handle_RC elif cmd == 0x20: - cmd_name = 'CMD: W_TX_PAYLOAD (WTP)' - cmd_hnd = self.handle_WTP - + cmd_name, cmd_hnd = 'CMD: W_TX_PAYLOAD (WTP)', self.handle_WTP elif cmd == 0x21: - cmd_name = 'CMD: R_TX_PAYLOAD (RTP)' - cmd_hnd = self.handle_RTP - + cmd_name, cmd_hnd = 'CMD: R_TX_PAYLOAD (RTP)', self.handle_RTP elif cmd == 0x22: - cmd_name = 'CMD: W_TX_ADDRESS (WTA)' - cmd_hnd = self.handle_WTA - + cmd_name, cmd_hnd = 'CMD: W_TX_ADDRESS (WTA)', self.handle_WTA elif cmd == 0x23: - cmd_name = 'CMD: R_TX_ADDRESS (RTA)' - cmd_hnd = self.handle_RTA - + cmd_name, cmd_hnd = 'CMD: R_TX_ADDRESS (RTA)', self.handle_RTA elif cmd == 0x24: - cmd_name = 'CMD: R_RX_PAYLOAD (RRP)' - cmd_hnd = self.handle_RRP - + cmd_name, cmd_hnd = 'CMD: R_RX_PAYLOAD (RRP)', self.handle_RRP elif (cmd & 0xF0 == 0x80): - cmd_name = 'CMD: CHANNEL_CONFIG (CC)' - cmd_hnd = self.handle_CC + cmd_name, cmd_hnd = 'CMD: CHANNEL_CONFIG (CC)', self.handle_CC # Report command name. self.put(self.cmd_samples['ss'], self.cmd_samples['es'], - self.out_ann, [self.ann_cmd, [cmd_name]]) + self.out_ann, [Ann.CMD, [cmd_name]]) # Handle status byte. self.handle_STAT()