X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fmrf24j40%2Fpd.py;h=db3ca98e93b4b017feaf7d9eed298ccad9406104;hb=3f5f3a92889e2f297ee6b94362e587a2994f896b;hp=286fa52403a4bd78d0c638cea2176a63a66de39e;hpb=07505b2a1a31759f90f9e7e2bfee5d75d4b1b729;p=libsigrokdecode.git diff --git a/decoders/mrf24j40/pd.py b/decoders/mrf24j40/pd.py index 286fa52..db3ca98 100644 --- a/decoders/mrf24j40/pd.py +++ b/decoders/mrf24j40/pd.py @@ -14,39 +14,59 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd from .lists import * +TX, RX = range(2) + class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'mrf24j40' name = 'MRF24J40' longname = 'Microchip MRF24J40' desc = 'IEEE 802.15.4 2.4 GHz RF tranceiver chip.' - license = 'gplv2' + license = 'gplv2+' inputs = ['spi'] - outputs = ['mrf24j40'] + outputs = [] + tags = ['IC', 'Wireless/RF'] annotations = ( ('sread', 'Short register read commands'), ('swrite', 'Short register write commands'), ('lread', 'Long register read commands'), ('lwrite', 'Long register write commands'), ('warning', 'Warnings'), + ('tx-frame', 'TX frame'), + ('rx-frame', 'RX frame'), + ('tx-retry-1', '1x TX retry'), + ('tx-retry-2', '2x TX retry'), + ('tx-retry-3', '3x TX retry'), + ('tx-fail', 'TX fail (too many retries)'), + ('ccafail', 'CCAFAIL (channel busy)'), ) annotation_rows = ( ('read', 'Read', (0, 2)), ('write', 'Write', (1, 3)), ('warnings', 'Warnings', (4,)), + ('tx-frames', 'TX frames', (5,)), + ('rx-frames', 'RX frames', (6,)), + ('tx-retries-1', '1x TX retries', (7,)), + ('tx-retries-2', '2x TX retries', (8,)), + ('tx-retries-3', '3x TX retries', (9,)), + ('tx-fails', 'TX fails', (10,)), + ('ccafails', 'CCAFAILs', (11,)), ) - def __init__(self, **kwargs): + def __init__(self): + self.reset() + + def reset(self): self.ss_cmd, self.es_cmd = 0, 0 - self.mosi_bytes = [] - self.miso_bytes = [] + self.ss_frame, self.es_frame = [0, 0], [0, 0] + self.mosi_bytes, self.miso_bytes = [], [] + self.framecache = [[], []] def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -57,7 +77,7 @@ class Decoder(srd.Decoder): def putw(self, pos, msg): self.put(pos[0], pos[1], self.out_ann, [4, [msg]]) - def reset(self): + def reset_data(self): self.mosi_bytes = [] self.miso_bytes = [] @@ -65,10 +85,34 @@ class Decoder(srd.Decoder): write = self.mosi_bytes[0] & 0x1 reg = (self.mosi_bytes[0] >> 1) & 0x3f reg_desc = sregs.get(reg, 'illegal') + for rxtx in (RX, TX): + if self.framecache[rxtx] == []: + continue + bit0 = self.mosi_bytes[1] & (1 << 0) + if rxtx == TX and not (reg_desc == 'TXNCON' and bit0 == 1): + continue + if rxtx == RX and not (reg_desc == 'RXFLUSH' and bit0 == 1): + continue + idx = 5 if rxtx == TX else 6 + xmitdir = 'TX' if rxtx == TX else 'RX' + frame = ' '.join(['%02X' % b for b in self.framecache[rxtx]]) + self.put(self.ss_frame[rxtx], self.es_frame[rxtx], self.out_ann, + [idx, ['%s frame: %s' % (xmitdir, frame)]]) + self.framecache[rxtx] = [] if write: self.putx([1, ['%s: %#x' % (reg_desc, self.mosi_bytes[1])]]) else: self.putx([0, ['%s: %#x' % (reg_desc, self.miso_bytes[1])]]) + numretries = (self.miso_bytes[1] & 0xc0) >> 6 + if reg_desc == 'TXSTAT' and numretries > 0: + txfail = 1 if ((self.miso_bytes[1] & (1 << 0)) != 0) else 0 + idx = 6 + numretries + txfail + if txfail: + self.putx([idx, ['TX fail (>= 4 retries)', 'TX fail']]) + else: + self.putx([idx, ['TX retries: %d' % numretries]]) + if reg_desc == 'TXSTAT' and (self.miso_bytes[1] & (1 << 5)) != 0: + self.putx([11, ['CCAFAIL (channel busy)', 'CCAFAIL']]) def handle_long(self): dword = self.mosi_bytes[0] << 8 | self.mosi_bytes[1] @@ -96,6 +140,16 @@ class Decoder(srd.Decoder): else: self.putx([2, ['%s: %#x' % (reg_desc, self.miso_bytes[2])]]) + for rxtx in (RX, TX): + if rxtx == RX and reg_desc[:3] != 'RX:': + continue + if rxtx == TX and reg_desc[:3] != 'TX:': + continue + if len(self.framecache[rxtx]) == 0: + self.ss_frame[rxtx] = self.ss_cmd + self.es_frame[rxtx] = self.es_cmd + self.framecache[rxtx] += [self.mosi_bytes[2]] if rxtx == TX else [self.miso_bytes[2]] + def decode(self, ss, es, data): ptype = data[0] if ptype == 'CS-CHANGE': @@ -104,7 +158,7 @@ class Decoder(srd.Decoder): if cs_old is not None and cs_old == 0 and cs_new == 1: if len(self.mosi_bytes) not in (0, 2, 3): self.putw([self.ss_cmd, es], 'Misplaced CS!') - self.reset() + self.reset_data() return # Don't care about anything else. @@ -127,8 +181,8 @@ class Decoder(srd.Decoder): if len(self.mosi_bytes) == 3: self.es_cmd = es self.handle_long() - self.reset() + self.reset_data() else: self.es_cmd = es self.handle_short() - self.reset() + self.reset_data()