X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fmicrowire%2Fpd.py;h=6650f383d2d57408cf283d84ca653893f9d556c6;hb=ad37302991cd5690bd1eb4db4abcad206fae42ec;hp=b8b18e8a2e57651963b3b89dc533b511e58f84e7;hpb=9fb04bdfa4a2fe0e5653d5922307696e29387dc0;p=libsigrokdecode.git

diff --git a/decoders/microwire/pd.py b/decoders/microwire/pd.py
index b8b18e8..6650f38 100644
--- a/decoders/microwire/pd.py
+++ b/decoders/microwire/pd.py
@@ -25,7 +25,7 @@ OUTPUT_PYTHON format:
 
 Packet:
 [namedtuple('ss': bit start sample number,
-  'se': bit end sample number,
+  'es': bit end sample number,
   'si': SI bit,
   'so': SO bit,
  ), ...]
@@ -38,7 +38,7 @@ To be able to annotate correctly the instructions formed by the bit, the start
 and end sample number of each bit (pair of SI/SO bit) are provided.
 '''
 
-PyPacket = namedtuple('PyPacket', 'ss se si so')
+PyPacket = namedtuple('PyPacket', 'ss es si so')
 Packet = namedtuple('Packet', 'samplenum matched cs sk si so')
 
 class Decoder(srd.Decoder):
@@ -50,6 +50,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['microwire']
+    tags = ['Embedded/industrial']
     channels = (
         {'id': 'cs', 'name': 'CS', 'desc': 'Chip select'},
         {'id': 'sk', 'name': 'SK', 'desc': 'Clock'},
@@ -71,6 +72,12 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (5,)),
     )
 
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
+        pass
+
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)