X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fmcs48%2Fpd.py;h=8c52de93e5b1af6f4bfc8e8c17f63d9b054d0ea1;hb=76de503871ada561290040204d3d8188b1ace336;hp=185fd89437ebde3197737d0688ce241855c30c9e;hpb=52e8d8b7548f7fdc2fe56bc133fe60b8147fb3b8;p=libsigrokdecode.git

diff --git a/decoders/mcs48/pd.py b/decoders/mcs48/pd.py
index 185fd89..8c52de9 100644
--- a/decoders/mcs48/pd.py
+++ b/decoders/mcs48/pd.py
@@ -18,6 +18,10 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Ann = SrdIntEnum.from_str('Ann', 'ROMDATA')
+Bin = SrdIntEnum.from_str('Bin', 'ROMDATA')
 
 class ChannelError(Exception):
     pass
@@ -30,7 +34,8 @@ class Decoder(srd.Decoder):
     desc = 'Intel MCS-48 external memory access protocol.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['mcs48']
+    outputs = []
+    tags = ['Retro computing']
     channels = (
         {'id': 'ale', 'name': 'ALE', 'desc': 'Address latch enable'},
         {'id': 'psen', 'name': '/PSEN', 'desc': 'Program store enable'},
@@ -94,10 +99,10 @@ class Decoder(srd.Decoder):
         self.data_s = self.samplenum
         if self.started:
             anntext = '{:04X}:{:02X}'.format(self.addr, self.data)
-            self.put(self.addr_s, self.data_s, self.out_ann, [0, [anntext]])
+            self.put(self.addr_s, self.data_s, self.out_ann, [Ann.ROMDATA, [anntext]])
             bindata = self.addr.to_bytes(2, byteorder='big')
             bindata += self.data.to_bytes(1, byteorder='big')
-            self.put(self.addr_s, self.data_s, self.out_bin, [0, bindata])
+            self.put(self.addr_s, self.data_s, self.out_bin, [Bin.ROMDATA, bindata])
 
     def decode(self):
         # Address bits above A11 are optional, and are considered to be A12+.