X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fmaple_bus%2Fpd.py;h=e0dcca736f95f155c6265267a230d3b80cfd52b2;hb=db18ba49bcbe38a9a67297207d821bf0e1e9dc4c;hp=f55872297ad0978a7ac8df87db8b285989f5d462;hpb=4cd8ac1d40f4c6af1be33033e0bd64b124dfce1e;p=libsigrokdecode.git

diff --git a/decoders/maple_bus/pd.py b/decoders/maple_bus/pd.py
index f558722..e0dcca7 100644
--- a/decoders/maple_bus/pd.py
+++ b/decoders/maple_bus/pd.py
@@ -18,6 +18,9 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'SDCKA SDCKB')
 
 ann = [
     ['Size', 'L'],
@@ -36,7 +39,8 @@ class Decoder(srd.Decoder):
     desc = 'Maple bus peripheral protocol for SEGA Dreamcast.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['maple_bus']
+    outputs = []
+    tags = ['Retro computing']
     channels = (
         {'id': 'sdcka', 'name': 'SDCKA', 'desc': 'Data/clock line A'},
         {'id': 'sdckb', 'name': 'SDCKB', 'desc': 'Data/clock line B'},
@@ -73,6 +77,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         pass
 
     def start(self):
@@ -80,26 +87,32 @@ class Decoder(srd.Decoder):
         self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.pending_bit_pos = None
 
+    def putx(self, data):
+        self.put(self.ss, self.es, self.out_ann, data)
+
+    def putb(self, data):
+        self.put(self.ss, self.es, self.out_binary, data)
+
     def byte_annotation(self, bintype, d):
         return [bintype + 6,
             ['%s: %02X' % (name, d) for name in ann[bintype]] + ['%02X' % d]]
 
     def got_start(self):
-        self.put(self.ss, self.es, self.out_ann, [0, ['Start pattern', 'Start', 'S']])
+        self.putx([0, ['Start pattern', 'Start', 'S']])
 
     def got_end(self):
-        self.put(self.ss, self.es, self.out_ann, [1, ['End pattern', 'End', 'E']])
+        self.putx([1, ['End pattern', 'End', 'E']])
         if self.length != self.expected_length + 1:
-            self.put(self.ss, self.es, self.out_ann, [14, ['Size error', 'L error', 'LE']])
+            self.putx([14, ['Size error', 'L error', 'LE']])
 
     def got_start_with_crc(self):
-        self.put(self.ss, self.es, self.out_ann, [2, ['Start pattern with CRC', 'Start CRC', 'SC']])
+        self.putx([2, ['Start pattern with CRC', 'Start CRC', 'SC']])
 
     def got_occupancy(self):
-        self.put(self.ss, self.es, self.out_ann, [3, ['SDCKB occupancy pattern', 'Occupancy', 'O']])
+        self.putx([3, ['SDCKB occupancy pattern', 'Occupancy', 'O']])
 
     def got_reset(self):
-        self.put(self.ss, self.es, self.out_ann, [4, ['RESET pattern', 'RESET', 'R']])
+        self.putx([4, ['RESET pattern', 'RESET', 'R']])
 
     def output_pending_bit(self):
         if self.pending_bit_pos:
@@ -121,22 +134,22 @@ class Decoder(srd.Decoder):
         elif self.length == self.expected_length:
             bintype = 5
             if self.data != self.checksum:
-                self.put(self.ss, self.es, self.out_ann, [13, ['Cksum error', 'K error', 'KE']])
+                self.putx([13, ['Cksum error', 'K error', 'KE']])
         self.length = self.length + 1
         self.checksum = self.checksum ^ self.data
-        self.put(self.ss, self.es, self.out_ann, self.byte_annotation(bintype, self.data))
-        self.put(self.ss, self.es, self.out_binary, [bintype, bytes([self.data])])
+        self.putx(self.byte_annotation(bintype, self.data))
+        self.putb([bintype, bytes([self.data])])
         self.pending_bit_pos = None
 
     def frame_error(self):
-        self.put(self.ss, self.es, self.out_ann, [7, ['Frame error', 'F error', 'FE']])
+        self.putx([7, ['Frame error', 'F error', 'FE']])
 
     def handle_start(self):
-        self.wait({0: 'l', 1: 'h'})
+        self.wait({Pin.SDCKA: 'l', Pin.SDCKB: 'h'})
         self.ss = self.samplenum
         count = 0
         while True:
-            sdcka, sdckb = self.wait([{1: 'f'}, {0: 'r'}])
+            sdcka, sdckb = self.wait([{Pin.SDCKB: 'f'}, {Pin.SDCKA: 'r'}])
             if self.matched[0]:
                 count = count + 1
             if self.matched[1]:
@@ -165,14 +178,15 @@ class Decoder(srd.Decoder):
         countb = 0
         self.data = 0
         while countb < 4:
-            sdcka, sdckb = self.wait([{0: 'f'}, {1: 'f'}])
+            sdcka, sdckb = self.wait([{Pin.SDCKA: 'f'}, {Pin.SDCKB: 'f'}])
             self.es = self.samplenum
             if self.matched[0]:
                 if counta == countb:
                     self.got_bit(sdckb)
                     counta = counta + 1
                 elif counta == 1 and countb == 0 and self.data == 0 and sdckb == 0:
-                    self.wait([{0: 'h', 1: 'h'}, {0: 'f'}, {1: 'f'}])
+                    self.wait([{Pin.SDCKA: 'h', Pin.SDCKB: 'h'},
+                               {Pin.SDCKA: 'f'}, {Pin.SDCKB: 'f'}])
                     self.es = self.samplenum
                     if self.matched[0]:
                         self.got_end()
@@ -192,7 +206,7 @@ class Decoder(srd.Decoder):
                 else:
                     self.frame_error()
                     return False
-        self.wait({0: 'h'})
+        self.wait({Pin.SDCKA: 'h'})
         self.es = self.samplenum
         self.got_byte()
         return True