X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Flpc%2Fpd.py;h=7153110a91c4cf91333014c9ad386802087b1665;hb=21e7a67e9a9d70aca44577d7556c1008e872d14c;hp=60399a52e0138c120b7d51d972b6c3621111da15;hpb=f7aa0719c59029f5340ac30d11efd5679ca07475;p=libsigrokdecode.git diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py index 60399a5..7153110 100644 --- a/decoders/lpc/pd.py +++ b/decoders/lpc/pd.py @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# LPC protocol decoder - import sigrokdecode as srd # ... @@ -107,33 +105,37 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['lpc'] probes = [ - {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'}, - {'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'}, - {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'}, - {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'}, - {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'}, - {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'}, + {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'}, + {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'}, + {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'}, + {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'}, + {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'}, + {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'}, ] optional_probes = [ - {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'}, - {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'}, - {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'}, - {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'}, - {'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'}, - {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'}, - {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'}, + {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'}, + {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'}, + {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'}, + {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'Clock run'}, + {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'}, + {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'}, + {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'}, ] options = {} annotations = [ ['warnings', 'Warnings'], ['start', 'Start'], - ['cycle_type', 'Cycle-type/direction'], + ['cycle-type', 'Cycle-type/direction'], ['addr', 'Address'], ['tar1', 'Turn-around cycle 1'], ['sync', 'Sync'], ['data', 'Data'], ['tar2', 'Turn-around cycle 2'], ] + annotation_rows = ( + ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)), + ('warnings', 'Warnings', (0,)), + ) def __init__(self, **kwargs): self.state = 'IDLE' @@ -148,16 +150,14 @@ class Decoder(srd.Decoder): self.tarcount = 0 self.synccount = 0 self.oldpins = None + self.ss_block = self.es_block = None - def start(self, metadata): - # self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc') - self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc') - - def report(self): - pass + def start(self): + # self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) def putb(self, data): - self.put(0, 0, self.out_ann, data) + self.put(self.ss_block, self.es_block, self.out_ann, data) def handle_get_start(self, lad, lad_bits, lframe): # LAD[3:0]: START field (1 clock cycle). @@ -166,8 +166,9 @@ class Decoder(srd.Decoder): # the peripherals must use. However, the host can keep LFRAME# asserted # multiple clocks, and we output all START fields that occur, even # though the peripherals are supposed to ignore all but the last one. - s = fields['START'][lad] - self.putb([1, [s]]) + self.es_block = self.samplenum + self.putb([1, [fields['START'][lad], 'START', 'St', 'S']]) + self.ss_block = self.samplenum # Output a warning if LAD[3:0] changes while LFRAME# is low. # TODO @@ -191,8 +192,9 @@ class Decoder(srd.Decoder): if self.cycle_type == 'Reserved': self.putb([0, ['Invalid cycle type (%s)' % lad_bits]]) - # ... + self.es_block = self.samplenum self.putb([2, ['Cycle type: %s' % self.cycle_type]]) + self.ss_block = self.samplenum self.state = 'GET ADDR' self.addr = 0 @@ -219,8 +221,10 @@ class Decoder(srd.Decoder): self.cur_nibble += 1 return + self.es_block = self.samplenum s = 'Address: 0x%%0%dx' % addr_nibbles self.putb([3, [s % self.addr]]) + self.ss_block = self.samplenum self.state = 'GET TAR' self.tar_count = 0 @@ -228,7 +232,9 @@ class Decoder(srd.Decoder): def handle_get_tar(self, lad, lad_bits): # LAD[3:0]: First TAR (turn-around) field (2 clock cycles). + self.es_block = self.samplenum self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]]) + self.ss_block = self.samplenum # On the first TAR clock cycle LAD[3:0] is driven to 1111 by # either the host or peripheral. On the second clock cycle, @@ -256,7 +262,9 @@ class Decoder(srd.Decoder): self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \ (self.synccount, self.sync_val)]]) + self.es_block = self.samplenum self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]]) + self.ss_block = self.samplenum # TODO @@ -278,7 +286,9 @@ class Decoder(srd.Decoder): self.cycle_count += 1 return + self.es_block = self.samplenum self.putb([6, ['DATA: 0x%02x' % self.databyte]]) + self.ss_block = self.samplenum self.cycle_count = 0 self.state = 'GET TAR2' @@ -286,7 +296,9 @@ class Decoder(srd.Decoder): def handle_get_tar2(self, lad, lad_bits): # LAD[3:0]: Second TAR field (2 clock cycles). + self.es_block = self.samplenum self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]]) + self.ss_block = self.samplenum # On the first TAR clock cycle LAD[3:0] is driven to 1111 by # either the host or peripheral. On the second clock cycle, @@ -304,7 +316,7 @@ class Decoder(srd.Decoder): self.state = 'IDLE' def decode(self, ss, es, data): - for (samplenum, pins) in data: + for (self.samplenum, pins) in data: # If none of the pins changed, there's nothing to do. if self.oldpins == pins: @@ -337,6 +349,7 @@ class Decoder(srd.Decoder): # A valid LPC cycle starts with LFRAME# being asserted (low). if lframe != 0: continue + self.ss_block = self.samplenum self.state = 'GET START' self.lad = -1 # self.clocknum = 0