X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Flpc%2Fpd.py;h=452e647118131428a5cebf42fcf22f0ab24f7858;hb=2842721f189c5338d268a6e70002936289ae6069;hp=08d0437affe9c04015ab2cfad40eea83cfe00364;hpb=6120ff64d4096bcb32c8a42f06ff77d75a5326c2;p=libsigrokdecode.git diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py index 08d0437..452e647 100644 --- a/decoders/lpc/pd.py +++ b/decoders/lpc/pd.py @@ -136,6 +136,9 @@ class Decoder(srd.Decoder): ) def __init__(self): + self.reset() + + def reset(self): self.state = 'IDLE' self.oldlclk = -1 self.samplenum = 0 @@ -182,10 +185,10 @@ class Decoder(srd.Decoder): def handle_get_ct_dr(self, lad, lad_bits): # LAD[3:0]: Cycle type / direction field (1 clock cycle). - self.cycle_type = fields['CT_DR'][lad] + self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown') # TODO: Warning/error on invalid cycle types. - if self.cycle_type == 'Reserved': + if 'Reserved' in self.cycle_type: self.putb([0, ['Invalid cycle type (%s)' % lad_bits]]) self.es_block = self.samplenum @@ -251,10 +254,10 @@ class Decoder(srd.Decoder): # LAD[3:0]: SYNC field (1-n clock cycles). self.sync_val = lad_bits - self.cycle_type = fields['SYNC'][lad] + self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown') # TODO: Warnings if reserved value are seen? - if self.cycle_type == 'Reserved': + if 'Reserved' in self.cycle_type: self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \ (self.synccount, self.sync_val)]]) @@ -337,7 +340,7 @@ class Decoder(srd.Decoder): # Most (but not all) states need this. if self.state != 'IDLE': lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0 - lad_bits = bin(lad)[2:].zfill(4) + lad_bits = '{:04b}'.format(lad) # self.putb([0, ['LAD: %s' % lad_bits]]) # TODO: Only memory read/write is currently supported/tested.