X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Flpc%2Fpd.py;h=08d0437affe9c04015ab2cfad40eea83cfe00364;hb=6120ff64d4096bcb32c8a42f06ff77d75a5326c2;hp=7153110a91c4cf91333014c9ad386802087b1665;hpb=58e7e508ded52194ed06a23a48f169779f4c7708;p=libsigrokdecode.git

diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py
index 7153110..08d0437 100644
--- a/decoders/lpc/pd.py
+++ b/decoders/lpc/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -96,7 +95,7 @@ fields = {
 }
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 3
     id = 'lpc'
     name = 'LPC'
     longname = 'Low-Pin-Count'
@@ -104,15 +103,15 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['lpc']
-    probes = [
+    channels = (
         {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
         {'id': 'lclk',   'name': 'LCLK',    'desc': 'Clock'},
         {'id': 'lad0',   'name': 'LAD[0]',  'desc': 'Addr/control/data 0'},
         {'id': 'lad1',   'name': 'LAD[1]',  'desc': 'Addr/control/data 1'},
         {'id': 'lad2',   'name': 'LAD[2]',  'desc': 'Addr/control/data 2'},
         {'id': 'lad3',   'name': 'LAD[3]',  'desc': 'Addr/control/data 3'},
-    ]
-    optional_probes = [
+    )
+    optional_channels = (
         {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'},
         {'id': 'ldrq',   'name': 'LDRQ#',   'desc': 'Encoded DMA / bus master request'},
         {'id': 'serirq', 'name': 'SERIRQ',  'desc': 'Serialized IRQ'},
@@ -120,28 +119,26 @@ class Decoder(srd.Decoder):
         {'id': 'lpme',   'name': 'LPME#',   'desc': 'LPC power management event'},
         {'id': 'lpcpd',  'name': 'LPCPD#',  'desc': 'Power down'},
         {'id': 'lsmi',   'name': 'LSMI#',   'desc': 'System Management Interrupt'},
-    ]
-    options = {}
-    annotations = [
-        ['warnings', 'Warnings'],
-        ['start', 'Start'],
-        ['cycle-type', 'Cycle-type/direction'],
-        ['addr', 'Address'],
-        ['tar1', 'Turn-around cycle 1'],
-        ['sync', 'Sync'],
-        ['data', 'Data'],
-        ['tar2', 'Turn-around cycle 2'],
-    ]
+    )
+    annotations = (
+        ('warnings', 'Warnings'),
+        ('start', 'Start'),
+        ('cycle-type', 'Cycle-type/direction'),
+        ('addr', 'Address'),
+        ('tar1', 'Turn-around cycle 1'),
+        ('sync', 'Sync'),
+        ('data', 'Data'),
+        ('tar2', 'Turn-around cycle 2'),
+    )
     annotation_rows = (
         ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)),
         ('warnings', 'Warnings', (0,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.state = 'IDLE'
         self.oldlclk = -1
         self.samplenum = 0
-        self.clocknum = 0
         self.lad = -1
         self.addr = 0
         self.cur_nibble = 0
@@ -153,7 +150,6 @@ class Decoder(srd.Decoder):
         self.ss_block = self.es_block = None
 
     def start(self):
-        # self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putb(self, data):
@@ -315,8 +311,10 @@ class Decoder(srd.Decoder):
         self.tarcount = 0
         self.state = 'IDLE'
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
+    def decode(self):
+        while True:
+            # TODO: Come up with more appropriate self.wait() conditions.
+            pins = self.wait()
 
             # If none of the pins changed, there's nothing to do.
             if self.oldpins == pins:
@@ -348,11 +346,10 @@ class Decoder(srd.Decoder):
             if self.state == 'IDLE':
                 # A valid LPC cycle starts with LFRAME# being asserted (low).
                 if lframe != 0:
-                   continue
+                    continue
                 self.ss_block = self.samplenum
                 self.state = 'GET START'
                 self.lad = -1
-                # self.clocknum = 0
             elif self.state == 'GET START':
                 self.handle_get_start(lad, lad_bits, lframe)
             elif self.state == 'GET CT/DR':
@@ -367,6 +364,3 @@ class Decoder(srd.Decoder):
                 self.handle_get_data(lad, lad_bits)
             elif self.state == 'GET TAR2':
                 self.handle_get_tar2(lad, lad_bits)
-            else:
-                raise Exception('Invalid state: %s' % self.state)
-