X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fjtag_stm32%2Fpd.py;h=10a098fa4276660b78bc1bec04e3252db8e9ca72;hb=a4dd548f5332453cef7442e453eef99343bdc5fb;hp=5dba78761dcd35c755da7601ebcf5096cf1f8a38;hpb=8915b34659332288aab38780d8f10d75c4c83e7f;p=libsigrokdecode.git

diff --git a/decoders/jtag_stm32/pd.py b/decoders/jtag_stm32/pd.py
index 5dba787..10a098f 100644
--- a/decoders/jtag_stm32/pd.py
+++ b/decoders/jtag_stm32/pd.py
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the libsigrokdecode project.
 ##
-## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# ST STM32 JTAG protocol decoder
-
 import sigrokdecode as srd
 
 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
@@ -121,7 +119,7 @@ def data_out(bits):
            % (data_hex, ack_meaning)
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'jtag_stm32'
     name = 'JTAG / STM32'
     longname = 'Joint Test Action Group / ST STM32'
@@ -129,23 +127,16 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['jtag']
     outputs = ['jtag_stm32']
-    probes = []
-    optional_probes = []
-    options = {}
-    annotations = [
-        ['Text', 'Human-readable text'],
-    ]
+    annotations = (
+        ('text', 'Human-readable text'),
+    )
 
     def __init__(self, **kwargs):
         self.state = 'IDLE'
-        # self.state = 'BYPASS'
+        self.samplenums = None
 
     def start(self):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
-
-    def report(self):
-        pass
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_reg_bypass(self, cmd, bits):
         # TODO
@@ -187,12 +178,20 @@ class Decoder(srd.Decoder):
                  [0, ['Unknown instruction: ' % bits]]) # TODO
 
     def decode(self, ss, es, data):
-        # Assumption: The right-most char in the 'val' bitstring is the LSB.
         cmd, val = data
 
         self.ss, self.es = ss, es
 
-        # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])
+        if cmd != 'NEW STATE':
+            val, self.samplenums = val
+
+            # The right-most char in the 'val' bitstring is the LSB.
+
+            # The STM32F10xxx has two serially connected JTAG TAPs, the
+            # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
+            # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
+            # Due to this, we need to ignore the last bit of each data shift.
+            val = val[:-1]
 
         # State machine
         if self.state == 'IDLE':
@@ -200,9 +199,10 @@ class Decoder(srd.Decoder):
             if cmd != 'IR TDI':
                 return
             # Switch to the state named after the instruction, or 'UNKNOWN'.
-            # Ignore bits other than IR[3:0]. While the IR register is only
-            # 4 bits in size, some programs (e.g. OpenOCD) might fill in a
-            # few more (dummy) bits. OpenOCD makes IR at least 8 bits long.
+            # The STM32F10xxx has two serially connected JTAG TAPs, the
+            # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
+            # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
+            # Currently we only care about the latter and use IR[3:0].
             self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
             self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
         elif self.state == 'BYPASS':
@@ -227,6 +227,3 @@ class Decoder(srd.Decoder):
             handle_reg(cmd, val)
             if cmd == 'DR TDO': # TODO: Assumes 'DR TDI' comes before 'DR TDO'
                 self.state = 'IDLE'
-        else:
-            raise Exception('Invalid state: %s' % self.state)
-