X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fjtag%2Fpd.py;h=25f26342183ba14bebc181fbeffeb85d4616ee58;hb=bf69977d12886794ac597083403859ac99ab38ac;hp=55a9a1f3498e495dc2d7ad54e63fb9ec0d5f1f6b;hpb=0c0368d0fc4ba737716326b87e99d70397134d38;p=libsigrokdecode.git

diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py
index 55a9a1f..25f2634 100644
--- a/decoders/jtag/pd.py
+++ b/decoders/jtag/pd.py
@@ -18,10 +18,30 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# JTAG protocol decoder
-
 import sigrokdecode as srd
 
+'''
+OUTPUT_PYTHON format:
+
+Packet:
+[<ptype>, <pdata>]
+
+<ptype>:
+ - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
+   Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
+   'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
+   'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
+   'EXIT2-IR', 'UPDATE-IR'.
+ - 'IR TDI': Bitstring that was clocked into the IR register.
+ - 'IR TDO': Bitstring that was clocked out of the IR register.
+ - 'DR TDI': Bitstring that was clocked into the DR register.
+ - 'DR TDO': Bitstring that was clocked out of the DR register.
+ - ...
+
+All bitstrings are a sequence of '1' and '0' characters. The right-most
+character in the bitstring is the LSB. Example: '01110001' (1 is LSB).
+'''
+
 jtag_states = [
         # Intro "tree"
         'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
@@ -33,14 +53,8 @@ jtag_states = [
         'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
 ]
 
-def get_annotation_classes():
-    l = []
-    for s in jtag_states:
-        l.append([s.lower(), s])
-    return l
-
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'jtag'
     name = 'JTAG'
     longname = 'Joint Test Action Group (IEEE 1149.1)'
@@ -48,19 +62,18 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['jtag']
-    probes = [
+    channels = (
         {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
         {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
         {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
         {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
-    ]
-    optional_probes = [
+    )
+    optional_channels = (
         {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
         {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
         {'id': 'rtck', 'name': 'RTCK',  'desc': 'Return clock signal'},
-    ]
-    options = {}
-    annotations = get_annotation_classes()
+    )
+    annotations = tuple([tuple([s.lower(), s]) for s in jtag_states])
 
     def __init__(self, **kwargs):
         # self.state = 'TEST-LOGIC-RESET'
@@ -76,14 +89,14 @@ class Decoder(srd.Decoder):
         self.first = True
 
     def start(self):
-        self.out_proto = self.register(srd.OUTPUT_PYTHON)
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putx(self, data):
         self.put(self.ss_item, self.es_item, self.out_ann, data)
 
     def putp(self, data):
-        self.put(self.ss_item, self.es_item, self.out_proto, data)
+        self.put(self.ss_item, self.es_item, self.out_python, data)
 
     def advance_state_machine(self, tms):
         self.oldstate = self.state
@@ -187,7 +200,7 @@ class Decoder(srd.Decoder):
             self.oldpins = pins
 
             # Get individual pin values into local variables.
-            # Unused probes will have a value of > 1.
+            # Unused channels will have a value of > 1.
             (tdi, tdo, tck, tms, trst, srst, rtck) = pins
 
             # We only care about TCK edges (either rising or falling).