X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fjitter%2Fpd.py;h=f492a9fa077c9027965a856b8809dabee2699191;hb=25d3576134e7b57ca169e8e4ebd4e4ce5dcf62dd;hp=d6db8e599cb8c1905f75db07c39e7d07a2e38815;hpb=70aa53ec10dabe4a5267e142974b35d1312f7119;p=libsigrokdecode.git

diff --git a/decoders/jitter/pd.py b/decoders/jitter/pd.py
index d6db8e5..f492a9f 100644
--- a/decoders/jitter/pd.py
+++ b/decoders/jitter/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -31,7 +30,7 @@ class SamplerateError(Exception):
     pass
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'jitter'
     name = 'Jitter'
     longname = 'Timing jitter calculation'
@@ -63,11 +62,13 @@ class Decoder(srd.Decoder):
         ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'CLK'
         self.samplerate = None
-        self.oldpin = None
-        self.oldclk = self.oldsig = None
+        self.oldclk, self.oldsig = 0, 0
         self.clk_start = None
         self.sig_start = None
         self.clk_missed = 0
@@ -77,7 +78,7 @@ class Decoder(srd.Decoder):
         self.clk_edge = edge_detector[self.options['clk_polarity']]
         self.sig_edge = edge_detector[self.options['sig_polarity']]
         self.out_ann = self.register(srd.OUTPUT_ANN)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_clk_missed = self.register(srd.OUTPUT_META,
             meta=(int, 'Clock missed', 'Clock transition missed'))
         self.out_sig_missed = self.register(srd.OUTPUT_META,
@@ -91,17 +92,17 @@ class Decoder(srd.Decoder):
     def putx(self, delta):
         # Adjust granularity.
         if delta == 0 or delta >= 1:
-            delta_s = u"%us" % (delta)
+            delta_s = '%.1fs' % (delta)
         elif delta <= 1e-12:
-            delta_s = u"%.1ffs" % (delta * 1e15)
+            delta_s = '%.1ffs' % (delta * 1e15)
         elif delta <= 1e-9:
-            delta_s = u"%.1fps" % (delta * 1e12)
+            delta_s = '%.1fps' % (delta * 1e12)
         elif delta <= 1e-6:
-            delta_s = u"%.1fns" % (delta * 1e9)
+            delta_s = '%.1fns' % (delta * 1e9)
         elif delta <= 1e-3:
-            delta_s = u"%.1fμs" % (delta * 1e6)
+            delta_s = '%.1fμs' % (delta * 1e6)
         else:
-            delta_s = u"%.1fms" % (delta * 1e3)
+            delta_s = '%.1fms' % (delta * 1e3)
 
         self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
 
@@ -111,8 +112,8 @@ class Decoder(srd.Decoder):
             return
         # Format the delta to an ASCII float value terminated by a newline.
         x = str(delta) + '\n'
-        self.put(self.clk_start, self.sig_start, self.out_bin,
-                 (0, x.encode('UTF-8')))
+        self.put(self.clk_start, self.sig_start, self.out_binary,
+                 [0, x.encode('UTF-8')])
 
     # Helper function for missed clock and signal annotations.
     def putm(self, data):
@@ -174,19 +175,12 @@ class Decoder(srd.Decoder):
             # everything we can with this sample.
             return True
 
-    def decode(self, ss, es, data):
+    def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
-
-        for (self.samplenum, pins) in data:
-            # We are only interested in transitions.
-            if self.oldpin == pins:
-                continue
-
-            self.oldpin, (clk, sig) = pins, pins
-
-            if self.oldclk is None and self.oldsig is None:
-                self.oldclk, self.oldsig = clk, sig
+        while True:
+            # Wait for a transition on CLK and/or SIG.
+            clk, sig = self.wait([{0: 'e'}, {1: 'e'}])
 
             # State machine:
             # For each sample we can move 2 steps forward in the state machine.