X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fjitter%2Fpd.py;h=f2fdb628b52f55aca2e03320048f3e651f9942dc;hb=05aaa48637fe56ac087569d784dbfdc91341f619;hp=0ddeea524dfd622d1502160e39d7524960a146f6;hpb=961699aaab1e44dab827c9f1884100b87a0a97fd;p=libsigrokdecode.git

diff --git a/decoders/jitter/pd.py b/decoders/jitter/pd.py
index 0ddeea5..f2fdb62 100644
--- a/decoders/jitter/pd.py
+++ b/decoders/jitter/pd.py
@@ -59,6 +59,9 @@ class Decoder(srd.Decoder):
         ('clk_missed', 'Clock missed', (1,)),
         ('sig_missed', 'Signal missed', (2,)),
     )
+    binary = (
+        ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
+    )
 
     def __init__(self, **kwargs):
         self.state = 'CLK'
@@ -74,6 +77,7 @@ class Decoder(srd.Decoder):
         self.clk_edge = edge_detector[self.options['clk_polarity']]
         self.sig_edge = edge_detector[self.options['sig_polarity']]
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_bin = self.register(srd.OUTPUT_BINARY)
         self.out_clk_missed = self.register(srd.OUTPUT_META,
             meta=(int, 'Clock missed', 'Clock transition missed'))
         self.out_sig_missed = self.register(srd.OUTPUT_META,
@@ -101,6 +105,15 @@ class Decoder(srd.Decoder):
 
         self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
 
+    # Helper function for ASCII float jitter values (one value per line).
+    def putb(self, delta):
+        if delta is None:
+            return
+        # Format the delta to an ASCII float output.
+        for x in str(delta):
+            self.put(self.clk_start, self.sig_start, self.out_bin, (0, bytes([ord(x)])))
+        self.put(self.clk_start, self.sig_start, self.out_bin, (0, bytes([ord('\n')])))
+
     # Helper function for missed clock and signal annotations.
     def putm(self, data):
         self.put(self.samplenum, self.samplenum, self.out_ann, data)
@@ -144,7 +157,9 @@ class Decoder(srd.Decoder):
             self.sig_start = self.samplenum
             self.state = 'CLK'
             # Calculate and report the timing jitter.
-            self.putx((self.sig_start - self.clk_start) / self.samplerate)
+            delta = (self.sig_start - self.clk_start) / self.samplerate
+            self.putx(delta)
+            self.putb(delta)
             return False
         else:
             if self.clk_start != self.samplenum \