X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fir_rc5%2Fpd.py;h=60a94160498a3beac0e74f31c1eec5b67c57d288;hb=fe9160d567fbb4c890ac7b8bc2e1f2f9143f0935;hp=ae20d3a70d11911ce7c7b615e8add19c2f065c75;hpb=92b7b49f6964f57a7d6fc4473645c993cfa4ba52;p=libsigrokdecode.git

diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py
index ae20d3a..60a9416 100644
--- a/decoders/ir_rc5/pd.py
+++ b/decoders/ir_rc5/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -25,7 +24,7 @@ class SamplerateError(Exception):
     pass
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'ir_rc5'
     name = 'IR RC-5'
     longname = 'IR RC-5'
@@ -57,6 +56,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.samplenum = None
         self.edges, self.bits, self.ss_es_bits = [], [], []
@@ -135,12 +137,12 @@ class Decoder(srd.Decoder):
         self.edges, self.bits, self.ss_es_bits = [], [], []
         self.state = 'IDLE'
 
-    def decode(self, ss, es, data):
+    def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
-        for (self.samplenum, pins) in data:
+        while True:
 
-            self.ir = pins[0]
+            (self.ir,) = self.wait()
 
             # Wait for any edge (rising or falling).
             if self.old_ir == self.ir:
@@ -148,8 +150,9 @@ class Decoder(srd.Decoder):
 
             # State machine.
             if self.state == 'IDLE':
+                bit = 1
                 self.edges.append(self.samplenum)
-                self.bits.append([self.samplenum, 1])
+                self.bits.append([self.samplenum, bit])
                 self.state = 'MID1'
                 self.old_ir = self.ir
                 continue