X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fir_nec%2Fpd.py;h=c05e4744dc6a76c06f3007c2387040bcfa71a096;hb=17e0ba228dadb7a12aa0e11fa81fcbc4a7836349;hp=ddc97d59648d6ffb23c170537df91ac096ae0e83;hpb=d478372a132d1872426f96f5f0d06119392805f7;p=libsigrokdecode.git diff --git a/decoders/ir_nec/pd.py b/decoders/ir_nec/pd.py index ddc97d5..c05e474 100644 --- a/decoders/ir_nec/pd.py +++ b/decoders/ir_nec/pd.py @@ -17,8 +17,9 @@ ## along with this program; if not, see . ## -import sigrokdecode as srd +from common.srdhelper import bitpack from .lists import * +import sigrokdecode as srd class SamplerateError(Exception): pass @@ -48,6 +49,8 @@ class Decoder(srd.Decoder): {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-low', 'values': ('active-low', 'active-high')}, {'id': 'cd_freq', 'desc': 'Carrier Frequency', 'default': 0}, + {'id': 'extended', 'desc': 'Extended NEC Protocol', + 'default': 'no', 'values': ('yes', 'no')}, ) annotations = ( ('bit', 'Bit'), @@ -77,16 +80,17 @@ class Decoder(srd.Decoder): def putb(self, data): self.put(self.ss_bit, self.samplenum, self.out_ann, data) - def putd(self, data): + def putd(self, data, bit_count): name = self.state.title() d = {'ADDRESS': Ann.ADDR, 'ADDRESS#': Ann.ADDR_INV, 'COMMAND': Ann.CMD, 'COMMAND#': Ann.CMD_INV} s = {'ADDRESS': ['ADDR', 'A'], 'ADDRESS#': ['ADDR#', 'A#'], 'COMMAND': ['CMD', 'C'], 'COMMAND#': ['CMD#', 'C#']} + fmt = '{{}}: 0x{{:0{}X}}'.format(bit_count // 4) self.putx([d[self.state], [ - '{}: 0x{:02X}'.format(name, data), - '{}: 0x{:02X}'.format(s[self.state][0], data), - '{}: 0x{:02X}'.format(s[self.state][1], data), + fmt.format(name, data), + fmt.format(s[self.state][0], data), + fmt.format(s[self.state][1], data), s[self.state][1], ]]) @@ -121,7 +125,7 @@ class Decoder(srd.Decoder): def reset(self): self.state = 'IDLE' self.ss_bit = self.ss_start = self.ss_other_edge = self.ss_remote = 0 - self.data = self.count = self.active = None + self.data = [] self.addr = self.cmd = None def start(self): @@ -151,26 +155,36 @@ class Decoder(srd.Decoder): ret = 1 if ret in (0, 1): self.putb([Ann.BIT, ['{:d}'.format(ret)]]) - self.data |= (ret << self.count) # LSB-first - self.count = self.count + 1 + self.data.append(ret) self.ss_bit = self.samplenum - def data_ok(self, check): + def data_ok(self, check, want_len): name = self.state.title() - valid = ((self.data >> 8) ^ (self.data & 0xff)) == 0xff - if self.count == 8: + normal, inverted = bitpack(self.data[:8]), bitpack(self.data[8:]) + valid = (normal ^ inverted) == 0xff + show = inverted if self.state.endswith('#') else normal + is_ext_addr = self.is_extended and self.state == 'ADDRESS' + if is_ext_addr: + normal = bitpack(self.data) + show = normal + valid = True + if len(self.data) == want_len: if self.state == 'ADDRESS': - self.addr = self.data + self.addr = normal if self.state == 'COMMAND': - self.cmd = self.data - self.putd(self.data) + self.cmd = normal + self.putd(show, want_len) self.ss_start = self.samplenum + if is_ext_addr: + self.data = [] + self.ss_bit = self.ss_start = self.samplenum return True if check and not valid: - self.putx([Ann.WARN, ['{} error: 0x{:04X}'.format(name, self.data)]]) + warn_show = bitpack(self.data) + self.putx([Ann.WARN, ['{} error: 0x{:04X}'.format(name, warn_show)]]) else: - self.putd(self.data >> 8) - self.data = self.count = 0 + self.putd(show, want_len) + self.data = [] self.ss_bit = self.ss_start = self.samplenum return valid @@ -184,7 +198,9 @@ class Decoder(srd.Decoder): cd_count = int(self.samplerate / self.options['cd_freq']) + 1 prev_ir = None - self.active = 0 if self.options['polarity'] == 'active-low' else 1 + active = 0 if self.options['polarity'] == 'active-low' else 1 + self.is_extended = self.options['extended'] == 'yes' + want_addr_len = 16 if self.is_extended else 8 while True: # Detect changes in the presence of an active input signal. @@ -203,7 +219,7 @@ class Decoder(srd.Decoder): if cd_count: (cur_ir,) = self.wait([{Pin.IR: 'e'}, {'skip': cd_count}]) if self.matched[0]: - cur_ir = self.active + cur_ir = active if cur_ir == prev_ir: continue prev_ir = cur_ir @@ -211,7 +227,7 @@ class Decoder(srd.Decoder): else: (self.ir,) = self.wait({Pin.IR: 'e'}) - if self.ir != self.active: + if self.ir != active: # Save the non-active edge, then wait for the next edge. self.ss_other_edge = self.samplenum continue @@ -224,33 +240,33 @@ class Decoder(srd.Decoder): self.putpause('Long') self.putx([Ann.LEADER_CODE, ['Leader code', 'Leader', 'LC', 'L']]) self.ss_remote = self.ss_start - self.data = self.count = 0 + self.data = [] self.state = 'ADDRESS' elif self.compare_with_tolerance(b, self.rc): self.putpause('Short') self.putstop(self.samplenum) self.samplenum += self.stop self.putx([Ann.REPEAT_CODE, ['Repeat code', 'Repeat', 'RC', 'R']]) - self.data = self.count = 0 + self.data = [] self.ss_bit = self.ss_start = self.samplenum elif self.state == 'ADDRESS': self.handle_bit(b) - if self.count == 8: - self.data_ok(False) - self.state = 'ADDRESS#' + if len(self.data) == want_addr_len: + self.data_ok(False, want_addr_len) + self.state = 'COMMAND' if self.is_extended else 'ADDRESS#' elif self.state == 'ADDRESS#': self.handle_bit(b) - if self.count == 16: - self.state = 'COMMAND' if self.data_ok(True) else 'IDLE' + if len(self.data) == 16: + self.state = 'COMMAND' if self.data_ok(True, 8) else 'IDLE' elif self.state == 'COMMAND': self.handle_bit(b) - if self.count == 8: - self.data_ok(False) + if len(self.data) == 8: + self.data_ok(False, 8) self.state = 'COMMAND#' elif self.state == 'COMMAND#': self.handle_bit(b) - if self.count == 16: - self.state = 'STOP' if self.data_ok(True) else 'IDLE' + if len(self.data) == 16: + self.state = 'STOP' if self.data_ok(True, 8) else 'IDLE' elif self.state == 'STOP': self.putstop(self.ss_bit) self.putremote()