X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fi2s%2Fi2s.py;h=b921011589bd3592824efb6d68ff5ad9b3b76561;hb=0afa64aefc96649c74770dbcbbcfb5934d99fe18;hp=30497b3190d0e02f26ba906a713729019e4cd439;hpb=2ab416c214e248be8ece49bab2cabf2b28954cca;p=libsigrokdecode.git diff --git a/decoders/i2s/i2s.py b/decoders/i2s/i2s.py index 30497b3..b921011 100644 --- a/decoders/i2s/i2s.py +++ b/decoders/i2s/i2s.py @@ -30,18 +30,19 @@ class Decoder(srd.Decoder): id = 'i2s' name = 'I2S' longname = 'Integrated Interchip Sound' - desc = 'I2S is an electrical serial bus interface standard used ' \ - 'for connecting digital audio devices together.' + desc = 'Serial bus for connecting digital audio devices.' license = 'gplv2+' inputs = ['logic'] outputs = ['i2s'] probes = [ {'id': 'sck', 'name': 'SCK', 'desc': 'Bit clock line'}, {'id': 'ws', 'name': 'WS', 'desc': 'Word select line'}, - {'id': 'sd', 'name': 'SD', 'desc': 'Serial Data line'}, + {'id': 'sd', 'name': 'SD', 'desc': 'Serial data line'}, ] + optional_probes = [] + options = {} annotations = [ - ['ASCII', 'Annotations in ASCII format'], + ['Hex', 'Annotations in hex format'], ] def __init__(self, **kwargs): @@ -50,15 +51,29 @@ class Decoder(srd.Decoder): self.bitcount = 0 self.data = 0 self.samplesreceived = 0 + self.first_sample = None self.start_sample = None self.samplenum = -1 + self.wordlength = -1 def start(self, metadata): + self.samplerate = metadata['samplerate'] self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2s') self.out_ann = self.add(srd.OUTPUT_ANN, 'i2s') def report(self): - return 'I2S: %d samples received' % self.samplesreceived + + # Calculate the sample rate. + samplerate = '?' + if self.start_sample != None and \ + self.first_sample != None and \ + self.start_sample > self.first_sample: + samplerate = '%d' % (self.samplesreceived * + self.samplerate / (self.start_sample - + self.first_sample)) + + return 'I2S: %d %d-bit samples received at %sHz' % \ + (self.samplesreceived, self.wordlength, samplerate) def decode(self, ss, es, data): for samplenum, (sck, ws, sd) in data: @@ -68,29 +83,42 @@ class Decoder(srd.Decoder): continue self.oldsck = sck - if sck == 0: # Ignore the falling clock edge + if sck == 0: # Ignore the falling clock edge. continue self.data = (self.data << 1) | sd self.bitcount += 1 - # This was not the LSB unless WS has flipped + # This was not the LSB unless WS has flipped. if ws == self.oldws: continue - # Only submit the sample, if we received the beginning of it + # Only submit the sample, if we received the beginning of it. if self.start_sample != None: self.samplesreceived += 1 self.put(self.start_sample, self.samplenum, self.out_proto, - ['data', self.data]) + ['data', self.data]) self.put(self.start_sample, self.samplenum, self.out_ann, - [ANN_HEX, ['%s %d-bits: 0x%08x' % ('L' if self.oldws else 'R', - self.bitcount, self.data)]]) + [ANN_HEX, ['%s: 0x%08x' % ('L' if self.oldws else 'R', + self.data)]]) + + # Check that the data word was the correct length. + if self.wordlength != -1 and self.wordlength != self.bitcount: + self.put(self.start_sample, self.samplenum, self.out_ann, + [ANN_HEX, ['WARNING: Received a %d-bit word, when a ' + '%d-bit word was expected' % (self.bitcount, + self.wordlength)]]) + + self.wordlength = self.bitcount # Reset decoder state. self.data = 0 self.bitcount = 0 self.start_sample = self.samplenum - + + # Save the first sample position. + if self.first_sample == None: + self.first_sample = self.samplenum + self.oldws = ws - \ No newline at end of file +