X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fi2c.py;h=e63ab8525454eb48ae10a2b244e01bb0862aa4b1;hb=876f83fd3396ce581e700741e58414c2f4f6277e;hp=edaeb9487b7c782c2479c2168ea5028907fd30d1;hpb=eb7082c98efad727d88e3ebeadcd496fa948475b;p=libsigrokdecode.git diff --git a/decoders/i2c.py b/decoders/i2c.py index edaeb94..e63ab85 100644 --- a/decoders/i2c.py +++ b/decoders/i2c.py @@ -22,7 +22,6 @@ # I2C protocol decoder # -# # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master # bus using two signals (SCL = serial clock line, SDA = serial data line). # @@ -69,28 +68,28 @@ # TODO: Handle multiple different I2C devices on same bus # -> we need to decode multiple protocols at the same time. -# -# I2C protocol output format: -# -# The protocol output consists of a (Python) list of I2C "packets", each of -# which is of the form -# -# [, , ] -# -# is one of: -# - 'START' (START condition) -# - 'START_REPEAT' (Repeated START) -# - 'ADDRESS_READ' (Slave address, read) -# - 'ADDRESS_WRITE' (Slave address, write) -# - 'DATA_READ' (Data, read) -# - 'DATA_WRITE' (Data, write) -# - 'STOP' (STOP condition) -# -# is the data or address byte associated with the ADDRESS_* and DATA_* -# command. For START, START_REPEAT and STOP, this is None. -# -# is either 'ACK' or 'NACK', but may also be None. -# +""" +I2C protocol output format: + +The protocol output consists of a (Python) list of I2C "packets", each of +which is of the form + + [ _i2c_command_, _data_, _ack_bit_ ] + +_i2c_command_ is one of: + - 'START' (START condition) + - 'START_REPEAT' (Repeated START) + - 'ADDRESS_READ' (Address, read) + - 'ADDRESS_WRITE' (Address, write) + - 'DATA_READ' (Data, read) + - 'DATA_WRITE' (Data, write) + - 'STOP' (STOP condition) + +_data_ is the data or address byte associated with the ADDRESS_* and DATA_* +command. For START, START_REPEAT and STOP, this is None. + +_ack_bit_ is either 'ACK' or 'NACK', but may also be None. +""" import sigrokdecode as srd @@ -102,14 +101,14 @@ ANN_RAW = 2 # Values are verbose and short annotation, respectively. protocol = { 'START': ['START', 'S'], - 'START_REPEAT': ['START REPEAT', 'Sr'], + 'START REPEAT': ['START REPEAT', 'Sr'], 'STOP': ['STOP', 'P'], 'ACK': ['ACK', 'A'], 'NACK': ['NACK', 'N'], - 'ADDRESS_READ': ['ADDRESS READ', 'AR'], - 'ADDRESS_WRITE': ['ADDRESS WRITE', 'AW'], - 'DATA_READ': ['DATA READ', 'DR'], - 'DATA_WRITE': ['DATA WRITE', 'DW'], + 'ADDRESS READ': ['ADDRESS READ', 'AR'], + 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'], + 'DATA READ': ['DATA READ', 'DR'], + 'DATA WRITE': ['DATA WRITE', 'DW'], } # States @@ -120,7 +119,7 @@ FIND_DATA = 2 class Decoder(srd.Decoder): id = 'i2c' name = 'I2C' - longname = 'Inter-Integrated Circuit (I2C) bus' + longname = 'Inter-Integrated Circuit' desc = 'I2C is a two-wire, multi-master, serial bus.' longdesc = '...' author = 'Uwe Hermann' @@ -133,7 +132,7 @@ class Decoder(srd.Decoder): {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, ] options = { - 'address-space': ['Address space (in bits)', 7], + 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10 } annotations = [ # ANN_SHIFTED @@ -157,6 +156,9 @@ class Decoder(srd.Decoder): self.oldscl = None self.oldsda = None + # Set protocol decoder option defaults. + self.addressing = Decoder.options['addressing'][1] + def start(self, metadata): self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c') self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c') @@ -183,10 +185,7 @@ class Decoder(srd.Decoder): return False def found_start(self, scl, sda): - if self.is_repeat_start == 1: - cmd = 'START_REPEAT' - else: - cmd = 'START' + cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' self.put(self.out_proto, [cmd, None, None]) self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]]) @@ -222,10 +221,7 @@ class Decoder(srd.Decoder): if self.state == FIND_ADDRESS: # The READ/WRITE bit is only in address bytes, not data bytes. - if self.databyte & 1: - self.wr = 0 - else: - self.wr = 1 + self.wr = 0 if (self.databyte & 1) else 1 d = self.databyte >> 1 elif self.state == FIND_DATA: d = self.databyte @@ -234,31 +230,22 @@ class Decoder(srd.Decoder): pass # Last bit that came in was the ACK/NACK bit (1 = NACK). - if sda == 1: - ack_bit = 'NACK' - else: - ack_bit = 'ACK' + ack_bit = 'NACK' if (sda == 1) else 'ACK' if self.state == FIND_ADDRESS and self.wr == 1: - cmd = 'ADDRESS_WRITE' + cmd = 'ADDRESS WRITE' elif self.state == FIND_ADDRESS and self.wr == 0: - cmd = 'ADDRESS_READ' + cmd = 'ADDRESS READ' elif self.state == FIND_DATA and self.wr == 1: - cmd = 'DATA_WRITE' + cmd = 'DATA WRITE' elif self.state == FIND_DATA and self.wr == 0: - cmd = 'DATA_READ' + cmd = 'DATA READ' self.put(self.out_proto, [cmd, d, ack_bit]) - self.put(self.out_ann, [ANN_SHIFTED, [ - '%s' % protocol[cmd][0], - '0x%02x' % d, - '%s' % protocol[ack_bit][0]] - ]) - self.put(self.out_ann, [ANN_SHIFTED_SHORT, [ - '%s' % protocol[cmd][1], - '0x%02x' % d, - '%s' % protocol[ack_bit][1]] - ]) + self.put(self.out_ann, [ANN_SHIFTED, + [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]]) + self.put(self.out_ann, [ANN_SHIFTED_SHORT, + [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]]) self.bitcount = self.databyte = 0 self.startsample = -1 @@ -284,7 +271,7 @@ class Decoder(srd.Decoder): # TODO: 0-0 sample range for now. super(Decoder, self).put(0, 0, output_id, data) - def decode(self, timeoffset, duration, data): + def decode(self, ss, es, data): for samplenum, (scl, sda) in data: self.samplecnt += 1