X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fi2c%2Fpd.py;h=82976627bdcc92ce972a181d426bc98fb596a034;hb=e144452bcdd5f2abbe6b6f3da41ad64f67e39def;hp=e226c24a41905ea55728b75bdc7d6278cc4be3d5;hpb=592f355b7fcf1cfb9e38d5d52373b6559ac26ecc;p=libsigrokdecode.git

diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py
index e226c24..8297662 100644
--- a/decoders/i2c/pd.py
+++ b/decoders/i2c/pd.py
@@ -14,12 +14,10 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
-# TODO: Implement support for 10bit slave addresses.
 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
 # TODO: Implement support for detecting various bus errors.
 
@@ -63,9 +61,6 @@ proto = {
     'DATA WRITE':      [9, 'Data write',    'DW'],
 }
 
-class SamplerateError(Exception):
-    pass
-
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'i2c'
@@ -75,6 +70,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['i2c']
+    tags = ['Embedded/industrial']
     channels = (
         {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
         {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
@@ -94,11 +90,11 @@ class Decoder(srd.Decoder):
         ('address-write', 'Address write'),
         ('data-read', 'Data read'),
         ('data-write', 'Data write'),
-        ('warnings', 'Human-readable warnings'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('bits', 'Bits', (5,)),
-        ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)),
+        ('addr-data', 'Address/data', (0, 1, 2, 3, 4, 6, 7, 8, 9)),
         ('warnings', 'Warnings', (10,)),
     )
     binary = (
@@ -109,6 +105,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.ss = self.es = self.ss_byte = -1
         self.bitcount = 0
@@ -131,10 +130,6 @@ class Decoder(srd.Decoder):
         self.out_bitrate = self.register(srd.OUTPUT_META,
                 meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
 
-        # Assume that the initial SCL/SDA pin state is high (logic 1).
-        # This is a good default, since both pins have pullups as per spec.
-        self.initial_pins = [1, 1]
-
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
@@ -241,9 +236,10 @@ class Decoder(srd.Decoder):
 
     def handle_stop(self, pins):
         # Meta bitrate
-        elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
-        bitrate = int(1 / elapsed * self.pdu_bits)
-        self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate)
+        if self.samplerate:
+            elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
+            bitrate = int(1 / elapsed * self.pdu_bits)
+            self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate)
 
         cmd = 'STOP'
         self.ss, self.es = self.samplenum, self.samplenum
@@ -255,11 +251,6 @@ class Decoder(srd.Decoder):
         self.bits = []
 
     def decode(self):
-        if not self.samplerate:
-            raise SamplerateError('Cannot decode without samplerate.')
-
-        self.wait({})
-
         while True:
             # State machine.
             if self.state == 'FIND START':
@@ -273,8 +264,7 @@ class Decoder(srd.Decoder):
                 #  a) Data sampling of receiver: SCL = rising, and/or
                 #  b) START condition (S): SCL = high, SDA = falling, and/or
                 #  c) STOP condition (P): SCL = high, SDA = rising
-                conds = [{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}]
-                pins = self.wait(conds[:]) # TODO
+                pins = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}])
 
                 # Check which of the condition(s) matched and handle them.
                 if self.matched[0]: