X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fi2c%2Fi2c.py;h=5f67d3576ab49d70eb0dbc15e107de67b3d8edea;hb=4180cba9a51acd32f69f0f8628bb746ea3e12be6;hp=5f952fae797f8539b53bf3272259a290a7344eee;hpb=1b75abfdd3e00ef590c9d1905863f6f2cb5a8632;p=libsigrokdecode.git

diff --git a/decoders/i2c/i2c.py b/decoders/i2c/i2c.py
index 5f952fa..5f67d35 100644
--- a/decoders/i2c/i2c.py
+++ b/decoders/i2c/i2c.py
@@ -38,7 +38,7 @@ ANN_SHIFTED_SHORT = 1
 ANN_RAW = 2
 
 # Values are verbose and short annotation, respectively.
-protocol = {
+proto = {
     'START':           ['START',         'S'],
     'START REPEAT':    ['START REPEAT',  'Sr'],
     'STOP':            ['STOP',          'P'],
@@ -50,12 +50,6 @@ protocol = {
     'DATA WRITE':      ['DATA WRITE',    'DW'],
 }
 
-# States
-FIND_START = 0
-FIND_ADDRESS = 1
-FIND_DATA = 2
-FIND_ACK = 3
-
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'i2c'
@@ -91,7 +85,7 @@ class Decoder(srd.Decoder):
         self.databyte = 0
         self.wr = -1
         self.is_repeat_start = 0
-        self.state = FIND_START
+        self.state = 'FIND START'
         self.oldscl = None
         self.oldsda = None
 
@@ -125,10 +119,10 @@ class Decoder(srd.Decoder):
 
         cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
         self.put(self.out_proto, [cmd, None])
-        self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
-        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
+        self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0]]])
+        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1]]])
 
-        self.state = FIND_ADDRESS
+        self.state = 'FIND ADDRESS'
         self.bitcount = self.databyte = 0
         self.is_repeat_start = 1
         self.wr = -1
@@ -154,48 +148,48 @@ class Decoder(srd.Decoder):
         # read/write and ACK/NACK bits.
         self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
 
-        if self.state == FIND_ADDRESS:
+        if self.state == 'FIND ADDRESS':
             # The READ/WRITE bit is only in address bytes, not data bytes.
             self.wr = 0 if (self.databyte & 1) else 1
             d = self.databyte >> 1
-        elif self.state == FIND_DATA:
+        elif self.state == 'FIND DATA':
             d = self.databyte
 
-        if self.state == FIND_ADDRESS and self.wr == 1:
+        if self.state == 'FIND ADDRESS' and self.wr == 1:
             cmd = 'ADDRESS WRITE'
-        elif self.state == FIND_ADDRESS and self.wr == 0:
+        elif self.state == 'FIND ADDRESS' and self.wr == 0:
             cmd = 'ADDRESS READ'
-        elif self.state == FIND_DATA and self.wr == 1:
+        elif self.state == 'FIND DATA' and self.wr == 1:
             cmd = 'DATA WRITE'
-        elif self.state == FIND_DATA and self.wr == 0:
+        elif self.state == 'FIND DATA' and self.wr == 0:
             cmd = 'DATA READ'
 
         self.put(self.out_proto, [cmd, d])
-        self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0], '0x%02x' % d]])
-        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1], '0x%02x' % d]])
+        self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0], '0x%02x' % d]])
+        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1], '0x%02x' % d]])
 
         # Done with this packet.
         self.startsample = -1
         self.bitcount = self.databyte = 0
-        self.state = FIND_ACK
+        self.state = 'FIND ACK'
 
     def get_ack(self, scl, sda):
         self.startsample = self.samplenum
         ack_bit = 'NACK' if (sda == 1) else 'ACK'
         self.put(self.out_proto, [ack_bit, None])
-        self.put(self.out_ann, [ANN_SHIFTED, [protocol[ack_bit][0]]])
-        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[ack_bit][1]]])
+        self.put(self.out_ann, [ANN_SHIFTED, [proto[ack_bit][0]]])
+        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[ack_bit][1]]])
         # There could be multiple data bytes in a row, so either find
         # another data byte or a STOP condition next.
-        self.state = FIND_DATA
+        self.state = 'FIND DATA'
 
     def found_stop(self, scl, sda):
         self.startsample = self.samplenum
         self.put(self.out_proto, ['STOP', None])
-        self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
-        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
+        self.put(self.out_ann, [ANN_SHIFTED, [proto['STOP'][0]]])
+        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto['STOP'][1]]])
 
-        self.state = FIND_START
+        self.state = 'FIND START'
         self.is_repeat_start = 0
         self.wr = -1
 
@@ -204,8 +198,7 @@ class Decoder(srd.Decoder):
         super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
 
     def decode(self, ss, es, data):
-        for samplenum, (scl, sda) in data:
-            self.samplenum = samplenum
+        for (self.samplenum, (scl, sda)) in data:
 
             # First sample: Save SCL/SDA value.
             if self.oldscl == None:
@@ -216,20 +209,20 @@ class Decoder(srd.Decoder):
             # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
 
             # State machine.
-            if self.state == FIND_START:
+            if self.state == 'FIND START':
                 if self.is_start_condition(scl, sda):
                     self.found_start(scl, sda)
-            elif self.state == FIND_ADDRESS:
+            elif self.state == 'FIND ADDRESS':
                 if self.is_data_bit(scl, sda):
                     self.found_address_or_data(scl, sda)
-            elif self.state == FIND_DATA:
+            elif self.state == 'FIND DATA':
                 if self.is_data_bit(scl, sda):
                     self.found_address_or_data(scl, sda)
                 elif self.is_start_condition(scl, sda):
                     self.found_start(scl, sda)
                 elif self.is_stop_condition(scl, sda):
                     self.found_stop(scl, sda)
-            elif self.state == FIND_ACK:
+            elif self.state == 'FIND ACK':
                 if self.is_data_bit(scl, sda):
                     self.get_ack(scl, sda)
             else: