X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fdsi%2Fpd.py;h=c5d9bf9c25c34c4f2d2375a577114f288ca6c5e8;hb=4f0d192d748e987af43ec5b811a643eb0a8601b2;hp=f2ca4be76ccb1059f8d3be2c1d6ba35ddbacb510;hpb=41b3732153c082f5a493514542e8963e6743b4e2;p=libsigrokdecode.git

diff --git a/decoders/dsi/pd.py b/decoders/dsi/pd.py
index f2ca4be..c5d9bf9 100644
--- a/decoders/dsi/pd.py
+++ b/decoders/dsi/pd.py
@@ -23,7 +23,7 @@ class SamplerateError(Exception):
     pass
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'dsi'
     name = 'DSI'
     longname = 'Digital Serial Interface'
@@ -40,23 +40,24 @@ class Decoder(srd.Decoder):
     )
     annotations = (
         ('bit', 'Bit'),
-        ('startbit', 'Startbit'),
-        ('Level', 'Dimmer level'),
+        ('startbit', 'Start bit'),
+        ('level', 'Dimmer level'),
         ('raw', 'Raw data'),
     )
     annotation_rows = (
         ('bits', 'Bits', (0,)),
-        ('raw', 'Raw Data',(3,)),
-        ('fields', 'Fields', (1, 2,)),
+        ('raw', 'Raw data', (3,)),
+        ('fields', 'Fields', (1, 2)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.samplenum = None
         self.edges, self.bits, self.ss_es_bits = [], [], []
         self.state = 'IDLE'
-        self.nextSamplePoint = None
-        self.nextSample = None
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
@@ -105,13 +106,12 @@ class Decoder(srd.Decoder):
         self.edges, self.bits, self.ss_es_bits = [], [], []
         self.state = 'IDLE'
 
-    def decode(self, ss, es, data):
+    def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
-        bit = 0;
-        for (self.samplenum, pins) in data:
-            self.dsi = pins[0]
-            # data.itercnt += 1
+        bit = 0
+        while True:
+            (self.dsi,) = self.wait()
             if self.options['polarity'] == 'active-high':
                 self.dsi ^= 1 # Invert.
 
@@ -128,15 +128,9 @@ class Decoder(srd.Decoder):
                 self.state = 'PHASE1'
                 self.old_dsi = self.dsi
                 # Get the next sample point.
-                # self.nextSamplePoint = self.samplenum + int(self.halfbit / 2)
                 self.old_dsi = self.dsi
-                # bit = self.dsi
                 continue
 
-            # if(self.samplenum == self.nextSamplePoint):
-            #    bit = self.dsi
-            #    continue
-
             if self.old_dsi != self.dsi:
                 self.edges.append(self.samplenum)
             elif self.samplenum == (self.edges[-1] + int(self.halfbit * 1.5)):
@@ -149,9 +143,9 @@ class Decoder(srd.Decoder):
                 self.phase0 = bit
                 self.state = 'PHASE1'
             elif self.state == 'PHASE1':
-                if (bit == 1) and (self.phase0 == 1): # Stop bit
+                if (bit == 1) and (self.phase0 == 1): # Stop bit.
                     if len(self.bits) == 17 or len(self.bits) == 9:
-                        # Forward or Backward
+                        # Forward or Backward.
                         self.handle_bits(len(self.bits))
                     self.reset_decoder_state() # Reset upon errors.
                     continue
@@ -159,6 +153,4 @@ class Decoder(srd.Decoder):
                     self.bits.append([self.edges[-3], bit])
                     self.state = 'PHASE0'
 
-            # self.nextSamplePoint = self.edges[-1] + int(self.halfbit / 2)
-
             self.old_dsi = self.dsi