X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fcjtag%2Fpd.py;h=cd4dc4e5864a3eef2337623b96f0a8311c30befa;hb=81bf080fdb9d6ef9b0357148a41e0610df75ab61;hp=885ececf636a1cabdf93e9d5a9d88abdcd3807b1;hpb=7aab31bb8a46aeaded3ba682cc3ebfc22a70dbcd;p=libsigrokdecode.git diff --git a/decoders/cjtag/pd.py b/decoders/cjtag/pd.py index 885ecec..cd4dc4e 100644 --- a/decoders/cjtag/pd.py +++ b/decoders/cjtag/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012-2015 Uwe Hermann +## Copyright (C) 2012-2020 Uwe Hermann ## Copyright (C) 2019 Zhiyuan Wan ## Copyright (C) 2019 Kongou Hikari ## @@ -20,6 +20,7 @@ ## import sigrokdecode as srd +from common.srdhelper import SrdStrEnum ''' OUTPUT_PYTHON format: @@ -44,16 +45,18 @@ of '1' and '0' characters (the right-most character is the LSB. Example: for each bit that is in the bitstring. ''' -jtag_states = [ - # Intro "tree" - 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', - # DR "tree" - 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR', - 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR', - # IR "tree" - 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR', - 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR', -] +s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \ + SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \ + SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR' +St = SrdStrEnum.from_str('St', s) + +jtag_states = [s.value for s in St] + +s = 'EC SPARE TPDEL TPREV TPST RDYC DLYC SCNFMT CP OAC'.split() +s = ['CJTAG_' + x for x in s] + ['OSCAN1', 'FOUR_WIRE'] +CSt = SrdStrEnum.from_list('CSt', s) + +cjtag_states = [s.value for s in CSt] class Decoder(srd.Decoder): api_version = 3 @@ -66,41 +69,36 @@ class Decoder(srd.Decoder): outputs = ['jtag'] tags = ['Debug/trace'] channels = ( - {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'}, - {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'}, - {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'}, - {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'}, - ) - optional_channels = ( - {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'}, - {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, - {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, + {'id': 'tckc', 'name': 'TCKC', 'desc': 'Test clock'}, + {'id': 'tmsc', 'name': 'TMSC', 'desc': 'Test mode select'}, ) - annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \ + annotations = \ + tuple([tuple([s.lower(), s]) for s in jtag_states]) + \ + tuple([tuple([s.lower(), s]) for s in cjtag_states]) + ( \ ('bit-tdi', 'Bit (TDI)'), ('bit-tdo', 'Bit (TDO)'), ('bitstring-tdi', 'Bitstring (TDI)'), ('bitstring-tdo', 'Bitstring (TDO)'), ('bit-tms', 'Bit (TMS)'), - ('state-tapc', 'TAPC state'), ) annotation_rows = ( - ('bits-tdi', 'Bits (TDI)', (16,)), - ('bits-tdo', 'Bits (TDO)', (17,)), - ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)), - ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)), - ('bits-tms', 'Bits (TMS)', (20,)), - ('states-tapc', 'TAPC states', (21,)), - ('states', 'States', tuple(range(15 + 1))), + ('bits-tdi', 'Bits (TDI)', (28,)), + ('bits-tdo', 'Bits (TDO)', (29,)), + ('bitstrings-tdi', 'Bitstrings (TDI)', (30,)), + ('bitstrings-tdo', 'Bitstrings (TDO)', (31,)), + ('bits-tms', 'Bits (TMS)', (32,)), + ('cjtag-states', 'CJTAG states', + tuple(range(len(jtag_states), len(jtag_states + cjtag_states)))), + ('jtag-states', 'JTAG states', tuple(range(len(jtag_states)))), ) def __init__(self): self.reset() def reset(self): - # self.state = 'TEST-LOGIC-RESET' - self.state = 'RUN-TEST/IDLE' - self.cjtagstate = '4-WIRE' + # self.state = St.TEST_LOGIC_RESET + self.state = St.RUN_TEST_IDLE + self.cjtagstate = CSt.FOUR_WIRE self.oldcjtagstate = None self.escape_edges = 0 self.oaclen = 0 @@ -137,80 +135,80 @@ class Decoder(srd.Decoder): def advance_state_machine(self, tms): self.oldstate = self.state - if self.cjtagstate.startswith('CJTAG-'): + if self.cjtagstate.value.startswith('CJTAG_'): self.oacp += 1 if self.oacp > 4 and self.oaclen == 12: - self.cjtagstate = 'CJTAG-EC' + self.cjtagstate = CSt.CJTAG_EC if self.oacp == 8 and tms == 0: self.oaclen = 36 if self.oacp > 8 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-SPARE' + self.cjtagstate = CSt.CJTAG_SPARE if self.oacp > 13 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-TPDEL' + self.cjtagstate = CSt.CJTAG_TPDEL if self.oacp > 16 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-TPREV' + self.cjtagstate = CSt.CJTAG_TPREV if self.oacp > 18 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-TPST' + self.cjtagstate = CSt.CJTAG_TPST if self.oacp > 23 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-RDYC' + self.cjtagstate = CSt.CJTAG_RDYC if self.oacp > 25 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-DLYC' + self.cjtagstate = CSt.CJTAG_DLYC if self.oacp > 27 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-SCNFMT' + self.cjtagstate = CSt.CJTAG_SCNFMT if self.oacp > 8 and self.oaclen == 12: - self.cjtagstate = 'CJTAG-CP' + self.cjtagstate = CSt.CJTAG_CP if self.oacp > 32 and self.oaclen == 36: - self.cjtagstate = 'CJTAG-CP' + self.cjtagstate = CSt.CJTAG_CP if self.oacp > self.oaclen: - self.cjtagstate = 'OSCAN1' + self.cjtagstate = CSt.OSCAN1 self.oscan1cycle = 1 # Because Nuclei cJTAG device asserts a reset during cJTAG # online activating. - self.state = 'TEST-LOGIC-RESET' + self.state = St.TEST_LOGIC_RESET return # Intro "tree" - if self.state == 'TEST-LOGIC-RESET': - self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE' - elif self.state == 'RUN-TEST/IDLE': - self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' + if self.state == St.TEST_LOGIC_RESET: + self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE + elif self.state == St.RUN_TEST_IDLE: + self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE # DR "tree" - elif self.state == 'SELECT-DR-SCAN': - self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR' - elif self.state == 'CAPTURE-DR': - self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR' - elif self.state == 'SHIFT-DR': - self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR' - elif self.state == 'EXIT1-DR': - self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR' - elif self.state == 'PAUSE-DR': - self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR' - elif self.state == 'EXIT2-DR': - self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR' - elif self.state == 'UPDATE-DR': - self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' + elif self.state == St.SELECT_DR_SCAN: + self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR + elif self.state == St.CAPTURE_DR: + self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR + elif self.state == St.SHIFT_DR: + self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR + elif self.state == St.EXIT1_DR: + self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR + elif self.state == St.PAUSE_DR: + self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR + elif self.state == St.EXIT2_DR: + self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR + elif self.state == St.UPDATE_DR: + self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE # IR "tree" - elif self.state == 'SELECT-IR-SCAN': - self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR' - elif self.state == 'CAPTURE-IR': - self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR' - elif self.state == 'SHIFT-IR': - self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR' - elif self.state == 'EXIT1-IR': - self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR' - elif self.state == 'PAUSE-IR': - self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR' - elif self.state == 'EXIT2-IR': - self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR' - elif self.state == 'UPDATE-IR': - self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' - - def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck): + elif self.state == St.SELECT_IR_SCAN: + self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR + elif self.state == St.CAPTURE_IR: + self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR + elif self.state == St.SHIFT_IR: + self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR + elif self.state == St.EXIT1_IR: + self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR + elif self.state == St.PAUSE_IR: + self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR + elif self.state == St.EXIT2_IR: + self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR + elif self.state == St.UPDATE_IR: + self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE + + def handle_rising_tckc_edge(self, tdi, tdo, tck, tms): # Rising TCK edges always advance the state machine. self.advance_state_machine(tms) @@ -223,23 +221,24 @@ class Decoder(srd.Decoder): # Output the saved item (from the last CLK edge to the current). self.es_item = self.samplenum # Output the old state (from last rising TCK edge to current one). - self.putx([jtag_states.index(self.oldstate), [self.oldstate]]) - self.putp(['NEW STATE', self.state]) + self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]]) + self.putp(['NEW STATE', self.state.value]) - self.putx([21, [self.oldcjtagstate]]) - if (self.oldcjtagstate.startswith('CJTAG-')): - self.putx([20, [str(self.oldtms)]]) + self.putx([len(jtag_states) + cjtag_states.index(self.oldcjtagstate.value), + [self.oldcjtagstate.value]]) + if (self.oldcjtagstate.value.startswith('CJTAG_')): + self.putx([32, [str(self.oldtms)]]) self.oldtms = tms # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values. - if self.oldstate.startswith('SHIFT-') or \ - self.oldstate.startswith('EXIT1-'): + if self.oldstate.value.startswith('SHIFT-') or \ + self.oldstate.value.startswith('EXIT1-'): if self.first_bit: self.ss_bitstring = self.samplenum self.first_bit = False else: - self.putx([16, [str(self.bits_tdi[0])]]) - self.putx([17, [str(self.bits_tdo[0])]]) + self.putx([28, [str(self.bits_tdi[0])]]) + self.putx([29, [str(self.bits_tdo[0])]]) # Use self.samplenum as ES of the previous bit. self.bits_samplenums_tdi[0][1] = self.samplenum self.bits_samplenums_tdo[0][1] = self.samplenum @@ -252,24 +251,24 @@ class Decoder(srd.Decoder): self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) # Output all TDI/TDO bits if we just switched to UPDATE-*. - if self.state.startswith('UPDATE-'): + if self.state.value.startswith('UPDATE-'): self.es_bitstring = self.samplenum - t = self.state[-2:] + ' TDI' + t = self.state.value[-2:] + ' TDI' b = ''.join(map(str, self.bits_tdi[1:])) h = ' (0x%x' % int('0b0' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits' - self.putx_bs([18, [s]]) + self.putx_bs([30, [s]]) self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]]) self.bits_tdi = [] self.bits_samplenums_tdi = [] - t = self.state[-2:] + ' TDO' + t = self.state.value[-2:] + ' TDO' b = ''.join(map(str, self.bits_tdo[1:])) h = ' (0x%x' % int('0b0' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits' - self.putx_bs([19, [s]]) + self.putx_bs([31, [s]]) self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]]) self.bits_tdo = [] self.bits_samplenums_tdo = [] @@ -280,47 +279,45 @@ class Decoder(srd.Decoder): self.ss_item = self.samplenum - def handle_tms_edge(self, tck, tms): + def handle_tmsc_edge(self): self.escape_edges += 1 - def handle_tapc_state(self, tck, tms): + def handle_tapc_state(self): self.oldcjtagstate = self.cjtagstate if self.escape_edges >= 8: - self.cjtagstate = '4-WIRE' + self.cjtagstate = CSt.FOUR_WIRE if self.escape_edges == 6: - self.cjtagstate = 'CJTAG-OAC' + self.cjtagstate = CSt.CJTAG_OAC self.oacp = 0 self.oaclen = 12 self.escape_edges = 0 def decode(self): - tdi_real = 0 - tms_real = 0 - tdo_real = 0 + tdi = tms = tdo = 0 while True: - # Wait for a rising edge on TCK. - (tdi, tdo, tck, tms, trst, srst, rtck) = self.wait({2: 'r'}) - self.handle_tapc_state(tck, tms) + # Wait for a rising edge on TCKC. + tckc, tmsc = self.wait({0: 'r'}) + self.handle_tapc_state() - if self.cjtagstate == 'OSCAN1': + if self.cjtagstate == CSt.OSCAN1: if self.oscan1cycle == 0: # nTDI - tdi_real = 1 if (tms == 0) else 0 + tdi = 1 if (tmsc == 0) else 0 self.oscan1cycle = 1 elif self.oscan1cycle == 1: # TMS - tms_real = tms + tms = tmsc self.oscan1cycle = 2 elif self.oscan1cycle == 2: # TDO - tdo_real = tms - self.handle_rising_tck_edge(tdi_real, tdo_real, tck, tms_real, trst, srst, rtck) + tdo = tmsc + self.handle_rising_tckc_edge(tdi, tdo, tckc, tms) self.oscan1cycle = 0 else: - self.handle_rising_tck_edge(tdi, tdo, tck, tms, trst, srst, rtck) + self.handle_rising_tckc_edge(None, None, tckc, tmsc) - while (tck == 1): - (tdi, tdo, tck, tms_n, trst, srst, rtck) = self.wait([{2: 'f'}, {3: 'e'}]) - if tms_n != tms: - tms = tms_n - self.handle_tms_edge(tck, tms) + while (tckc == 1): + tckc, tmsc_n = self.wait([{0: 'f'}, {1: 'e'}]) + if tmsc_n != tmsc: + tmsc = tmsc_n + self.handle_tmsc_edge()