X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fcjtag%2Fpd.py;h=2e7f493ce3c56850ad12a0783c50306f4d7f0742;hb=242438c32bfab01ae65ccc3678f5b9702a0678bb;hp=9849b3ab46b6f45b63199bd78c9813d0dbb079e3;hpb=d315969c893bb62dca66433877765a5092e7c33d;p=libsigrokdecode.git diff --git a/decoders/cjtag/pd.py b/decoders/cjtag/pd.py index 9849b3a..2e7f493 100644 --- a/decoders/cjtag/pd.py +++ b/decoders/cjtag/pd.py @@ -55,6 +55,12 @@ jtag_states = [ 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR', ] +cjtag_states = [ + 'CJTAG-EC', 'CJTAG-SPARE', 'CJTAG-TPDEL', 'CJTAG-TPREV', 'CJTAG-TPST', + 'CJTAG-RDYC', 'CJTAG-DLYC', 'CJTAG-SCNFMT', 'CJTAG-CP', 'CJTAG-OAC', + 'OSCAN1', '4-WIRE', +] + class Decoder(srd.Decoder): api_version = 3 id = 'cjtag' @@ -66,32 +72,27 @@ class Decoder(srd.Decoder): outputs = ['jtag'] tags = ['Debug/trace'] channels = ( - {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'}, - {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'}, - {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'}, - {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'}, - ) - optional_channels = ( - {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'}, - {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, - {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, + {'id': 'tckc', 'name': 'TCKC', 'desc': 'Test clock'}, + {'id': 'tmsc', 'name': 'TMSC', 'desc': 'Test mode select'}, ) - annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \ + annotations = \ + tuple([tuple([s.lower(), s]) for s in jtag_states]) + \ + tuple([tuple([s.lower(), s]) for s in cjtag_states]) + ( \ ('bit-tdi', 'Bit (TDI)'), ('bit-tdo', 'Bit (TDO)'), ('bitstring-tdi', 'Bitstring (TDI)'), ('bitstring-tdo', 'Bitstring (TDO)'), ('bit-tms', 'Bit (TMS)'), - ('state-tapc', 'TAPC state'), ) annotation_rows = ( - ('bits-tdi', 'Bits (TDI)', (16,)), - ('bits-tdo', 'Bits (TDO)', (17,)), - ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)), - ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)), - ('bits-tms', 'Bits (TMS)', (20,)), - ('states-tapc', 'TAPC states', (21,)), - ('states', 'States', tuple(range(15 + 1))), + ('bits-tdi', 'Bits (TDI)', (28,)), + ('bits-tdo', 'Bits (TDO)', (29,)), + ('bitstrings-tdi', 'Bitstrings (TDI)', (30,)), + ('bitstrings-tdo', 'Bitstrings (TDO)', (31,)), + ('bits-tms', 'Bits (TMS)', (32,)), + ('cjtag-states', 'CJTAG states', + tuple(range(len(jtag_states), len(jtag_states + cjtag_states)))), + ('jtag-states', 'JTAG states', tuple(range(len(jtag_states)))), ) def __init__(self): @@ -210,7 +211,7 @@ class Decoder(srd.Decoder): elif self.state == 'UPDATE-IR': self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' - def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck): + def handle_rising_tckc_edge(self, tdi, tdo, tck, tms): # Rising TCK edges always advance the state machine. self.advance_state_machine(tms) @@ -226,9 +227,10 @@ class Decoder(srd.Decoder): self.putx([jtag_states.index(self.oldstate), [self.oldstate]]) self.putp(['NEW STATE', self.state]) - self.putx([21, [self.oldcjtagstate]]) + self.putx([len(jtag_states) + cjtag_states.index(self.oldcjtagstate), + [self.oldcjtagstate]]) if (self.oldcjtagstate.startswith('CJTAG-')): - self.putx([20, [str(self.oldtms)]]) + self.putx([32, [str(self.oldtms)]]) self.oldtms = tms # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values. @@ -238,8 +240,8 @@ class Decoder(srd.Decoder): self.ss_bitstring = self.samplenum self.first_bit = False else: - self.putx([16, [str(self.bits_tdi[0])]]) - self.putx([17, [str(self.bits_tdo[0])]]) + self.putx([28, [str(self.bits_tdi[0])]]) + self.putx([29, [str(self.bits_tdo[0])]]) # Use self.samplenum as ES of the previous bit. self.bits_samplenums_tdi[0][1] = self.samplenum self.bits_samplenums_tdo[0][1] = self.samplenum @@ -260,7 +262,7 @@ class Decoder(srd.Decoder): b = ''.join(map(str, self.bits_tdi[1:])) h = ' (0x%x' % int('0b0' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits' - self.putx_bs([18, [s]]) + self.putx_bs([30, [s]]) self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]]) self.bits_tdi = [] self.bits_samplenums_tdi = [] @@ -269,7 +271,7 @@ class Decoder(srd.Decoder): b = ''.join(map(str, self.bits_tdo[1:])) h = ' (0x%x' % int('0b0' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits' - self.putx_bs([19, [s]]) + self.putx_bs([31, [s]]) self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]]) self.bits_tdo = [] self.bits_samplenums_tdo = [] @@ -280,10 +282,10 @@ class Decoder(srd.Decoder): self.ss_item = self.samplenum - def handle_tms_edge(self, tck, tms): + def handle_tmsc_edge(self): self.escape_edges += 1 - def handle_tapc_state(self, tck, tms): + def handle_tapc_state(self): self.oldcjtagstate = self.cjtagstate if self.escape_edges >= 8: @@ -301,29 +303,26 @@ class Decoder(srd.Decoder): tdo_real = 0 while True: - # Wait for a rising edge on TCK. - (tdi, tdo, tck, tms, trst, srst, rtck) = self.wait({2: 'r'}) - self.handle_tapc_state(tck, tms) + # Wait for a rising edge on TCKC. + tckc, tmsc = self.wait({0: 'r'}) + self.handle_tapc_state() if self.cjtagstate == 'OSCAN1': if self.oscan1cycle == 0: # nTDI - if tms == 0: - tdi_real = 1 - else: - tdi_real = 0 + tdi_real = 1 if (tmsc == 0) else 0 self.oscan1cycle = 1 elif self.oscan1cycle == 1: # TMS - tms_real = tms + tms_real = tmsc self.oscan1cycle = 2 elif self.oscan1cycle == 2: # TDO - tdo_real = tms - self.handle_rising_tck_edge(tdi_real, tdo_real, tck, tms_real, trst, srst, rtck) + tdo_real = tmsc + self.handle_rising_tckc_edge(tdi_real, tdo_real, tckc, tms_real) self.oscan1cycle = 0 else: - self.handle_rising_tck_edge(tdi, tdo, tck, tms, trst, srst, rtck) + self.handle_rising_tckc_edge(None, None, tckc, tmsc) - while (tck == 1): - (tdi, tdo, tck, tms_n, trst, srst, rtck) = self.wait([{2: 'f'}, {3: 'e'}]) - if tms_n != tms: - tms = tms_n - self.handle_tms_edge(tck, tms) + while (tckc == 1): + tckc, tmsc_n = self.wait([{0: 'f'}, {1: 'e'}]) + if tmsc_n != tmsc: + tmsc = tmsc_n + self.handle_tmsc_edge()