X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fcan%2Fpd.py;h=d76d649cc593bfeb7101f636cbb5b4d476d64619;hb=8a8b516aff4005faeea3df0f3ecb22527c10ae8d;hp=61b0a744cacb217f56a3ded29e95f6db9e49c5f9;hpb=74c9bb3caa945409b3e8a68920f910e8363732fb;p=libsigrokdecode.git diff --git a/decoders/can/pd.py b/decoders/can/pd.py index 61b0a74..d76d649 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -14,16 +14,16 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## -# CAN protocol decoder - import sigrokdecode as srd +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'can' name = 'CAN' longname = 'Controller Area Network' @@ -31,51 +31,58 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['can'] - probes = [ + channels = ( {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, - ] - optional_probes = [] - options = { - 'bitrate': ['Bitrate', 1000000], # 1Mbit/s - 'sample_point': ['Sample point', 70], # 70% - } - annotations = [ - ['Data', 'CAN payload data'], - ['SOF', 'Start of frame'], - ['EOF', 'End of frame'], - ['ID', 'Identifier'], - ['Ext. ID', 'Extended identifier'], - ['Full ID', 'Full identifier'], - ['IDE', 'Identifier extension bit'], - ['Reserved bit', 'Reserved bit 0 and 1'], - ['RTR', 'Remote transmission request'], - ['SRR', 'Substitute remote request'], - ['DLC', 'Data length count'], - ['CRC sequence', 'CRC sequence'], - ['CRC delimiter', 'CRC delimiter'], - ['ACK slot', 'ACK slot'], - ['ACK delimiter', 'ACK delimiter'], - ['Stuff bit', 'Stuff bit'], - ['Warnings', 'Human-readable warnings'], - ] - - def __init__(self, **kwargs): + ) + options = ( + {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000}, + {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, + ) + annotations = ( + ('data', 'CAN payload data'), + ('sof', 'Start of frame'), + ('eof', 'End of frame'), + ('id', 'Identifier'), + ('ext-id', 'Extended identifier'), + ('full-id', 'Full identifier'), + ('ide', 'Identifier extension bit'), + ('reserved-bit', 'Reserved bit 0 and 1'), + ('rtr', 'Remote transmission request'), + ('srr', 'Substitute remote request'), + ('dlc', 'Data length count'), + ('crc-sequence', 'CRC sequence'), + ('crc-delimiter', 'CRC delimiter'), + ('ack-slot', 'ACK slot'), + ('ack-delimiter', 'ACK delimiter'), + ('stuff-bit', 'Stuff bit'), + ('warnings', 'Human-readable warnings'), + ('bit', 'Bit'), + ) + annotation_rows = ( + ('bits', 'Bits', (15, 17)), + ('fields', 'Fields', tuple(range(15))), + ('warnings', 'Warnings', (16,)), + ) + + def __init__(self): + self.reset() + + def reset(self): + self.samplerate = None self.reset_variables() - def start(self, metadata): - # self.out_proto = self.add(srd.OUTPUT_PROTO, 'can') - self.out_ann = self.add(srd.OUTPUT_ANN, 'can') + def start(self): + self.out_ann = self.register(srd.OUTPUT_ANN) - self.samplerate = metadata['samplerate'] - self.bit_width = float(self.samplerate) / float(self.options['bitrate']) - self.bitpos = (self.bit_width / 100.0) * self.options['sample_point'] - - def report(self): - pass + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + self.bit_width = float(self.samplerate) / float(self.options['bitrate']) + self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] # Generic helper for CAN bit annotations. def putg(self, ss, es, data): - left, right = int(self.bitpos), int(self.bit_width - self.bitpos) + left, right = int(self.sample_point), int(self.bit_width - self.sample_point) self.put(ss - left, es + right, self.out_ann, data) # Single-CAN-bit annotation using the current samplenum. @@ -101,23 +108,37 @@ class Decoder(srd.Decoder): self.ss_bit12 = None self.ss_databytebits = [] - # Return True if we reached the desired bit position, False otherwise. - def reached_bit(self, bitnum): - bitpos = int(self.sof + (self.bit_width * bitnum) + self.bitpos) - if self.samplenum >= bitpos: - return True - return False + # Poor man's clock synchronization. Use signal edges which change to + # dominant state in rather simple ways. This naive approach is neither + # aware of the SYNC phase's width nor the specific location of the edge, + # but improves the decoder's reliability when the input signal's bitrate + # does not exactly match the nominal rate. + def dom_edge_seen(self, force = False): + self.dom_edge_snum = self.samplenum + self.dom_edge_bcount = self.curbit + + def bit_sampled(self): + # EMPTY + pass + + # Determine the position of the next desired bit's sample point. + def get_sample_point(self, bitnum): + samplenum = self.dom_edge_snum + samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount)) + samplenum += int(self.sample_point) + return samplenum def is_stuff_bit(self): # CAN uses NRZ encoding and bit stuffing. # After 5 identical bits, a stuff bit of opposite value is added. + # But not in the CRC delimiter, ACK, and end of frame fields. + if len(self.bits) > self.last_databit + 17: + return False last_6_bits = self.rawbits[-6:] if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): return False # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. - self.putx([15, ['Stuff bit: %d' % self.rawbits[-1], - 'SB: %d' % self.rawbits[-1], 'SB']]) self.bits.pop() # Drop last bit. return True @@ -153,6 +174,8 @@ class Decoder(srd.Decoder): elif bitnum == (self.last_databit + 16): self.putx([12, ['CRC delimiter: %d' % can_rx, 'CRC d: %d' % can_rx, 'CRC d']]) + if can_rx != 1: + self.putx([16, ['CRC delimiter must be a recessive bit']]) # ACK slot bit (dominant: ACK, recessive: NACK) elif bitnum == (self.last_databit + 17): @@ -163,6 +186,8 @@ class Decoder(srd.Decoder): elif bitnum == (self.last_databit + 18): self.putx([14, ['ACK delimiter: %d' % can_rx, 'ACK d: %d' % can_rx, 'ACK d']]) + if can_rx != 1: + self.putx([16, ['ACK delimiter must be a recessive bit']]) # Remember start of EOF (see below). elif bitnum == (self.last_databit + 19): @@ -171,6 +196,8 @@ class Decoder(srd.Decoder): # End of frame (EOF), 7 recessive bits elif bitnum == (self.last_databit + 25): self.putb([2, ['End of frame', 'EOF', 'E']]) + if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: + self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) self.reset_variables() return True @@ -202,6 +229,8 @@ class Decoder(srd.Decoder): self.putb([10, ['Data length code: %d' % self.dlc, 'DLC: %d' % self.dlc, 'DLC']]) self.last_databit = 18 + (self.dlc * 8) + if self.dlc > 8: + self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) # Remember all databyte bits, except the very last one. elif bitnum in range(19, self.last_databit): @@ -306,20 +335,18 @@ class Decoder(srd.Decoder): # Get the index of the current CAN frame bit (without stuff bits). bitnum = len(self.bits) - 1 - # For debugging. - # self.putx([0, ['Bit %d (CAN bit %d): %d' % \ - # (self.curbit, bitnum, can_rx)]]) - # If this is a stuff bit, remove it from self.bits and ignore it. if self.is_stuff_bit(): + self.putx([15, [str(can_rx)]]) self.curbit += 1 # Increase self.curbit (bitnum is not affected). return + else: + self.putx([17, [str(can_rx)]]) # Bit 0: Start of frame (SOF) bit if bitnum == 0: - if can_rx == 0: - self.putx([1, ['Start of frame', 'SOF', 'S']]) - else: + self.putx([1, ['Start of frame', 'SOF', 'S']]) + if can_rx != 0: self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) # Remember start of ID (see below). @@ -332,6 +359,8 @@ class Decoder(srd.Decoder): self.id = int(''.join(str(d) for d in self.bits[1:]), 2) s = '%d (0x%x)' % (self.id, self.id), self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) + if (self.id & 0x7f0) == 0x7f0: + self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) # RTR or SRR bit, depending on frame type (gets handled later). elif bitnum == 12: @@ -361,23 +390,24 @@ class Decoder(srd.Decoder): self.curbit += 1 - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: - - (can_rx,) = pins + def decode(self): + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') + while True: # State machine. if self.state == 'IDLE': # Wait for a dominant state (logic 0) on the bus. - if can_rx == 1: - continue + (can_rx,) = self.wait({0: 'l'}) self.sof = self.samplenum + self.dom_edge_seen(force = True) self.state = 'GET BITS' elif self.state == 'GET BITS': # Wait until we're in the correct bit/sampling position. - if not self.reached_bit(self.curbit): - continue - self.handle_bit(can_rx) - else: - raise Exception("Invalid state: %s" % self.state) - + pos = self.get_sample_point(self.curbit) + (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) + if self.matched[1]: + self.dom_edge_seen() + if self.matched[0]: + self.handle_bit(can_rx) + self.bit_sampled()