X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fadf435x%2Fpd.py;h=9ba88ca9c698d49907224c675a9a828ab5a36e9a;hb=adb8233a0bf30b1d9ee9176e1caa5dc8ae1830dd;hp=8f51ee245d43335feca823b9320ba5987ba98aca;hpb=1d4fe1c19c0948fb67b4a91495b126a763ea7adb;p=libsigrokdecode.git

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index 8f51ee2..9ba88ca 100644
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -86,25 +86,32 @@ regs = {
 }
 
 ANN_REG = 0
+ANN_WARN = 1
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'adf435x'
     name = 'ADF435x'
     longname = 'Analog Devices ADF4350/1'
     desc = 'Wideband synthesizer with integrated VCO.'
     license = 'gplv3+'
     inputs = ['spi']
-    outputs = ['adf435x']
+    outputs = []
+    tags = ['Clock/timing', 'IC', 'Wireless/RF']
     annotations = (
         # Sent from the host to the chip.
-        ('register', 'Register written to the device'),
+        ('write', 'Register write'),
+        ('warning', "Warnings"),
     )
     annotation_rows = (
-        ('registers', 'Register writes', (ANN_REG,)),
+        ('writes', 'Register writes', (ANN_REG,)),
+        ('warnings', 'Warnings', (ANN_WARN,)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.bits = []
 
     def start(self):
@@ -121,20 +128,23 @@ class Decoder(srd.Decoder):
         return val
 
     def decode(self, ss, es, data):
+        ptype, _, _ = data
 
-        ptype, data1, data2 = data
+        if ptype == 'TRANSFER':
+            if len(self.bits) == 32:
+                reg_value, reg_pos = self.decode_bits(0, 3)
+                self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
+                    ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
+                     '[%d]' % reg_value]])
+                if reg_value < len(regs):
+                    field_descs = regs[reg_value]
+                    for field_desc in field_descs:
+                        field = self.decode_field(*field_desc)
+            else:
+                error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
+                self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
+            self.bits = []
 
-        if ptype == 'CS-CHANGE':
-            if data1 == 1:
-                if len(self.bits) == 32:
-                    reg_value, reg_pos = self.decode_bits(0, 3)
-                    self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
-                        ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
-                         '[%d]' % reg_value]])
-                    if reg_value < len(regs):
-                        field_descs = regs[reg_value]
-                        for field_desc in field_descs:
-                            field = self.decode_field(*field_desc)
-                self.bits = []
         if ptype == 'BITS':
-            self.bits = data1 + self.bits
+            _, mosi_bits, miso_bits = data
+            self.bits = mosi_bits + self.bits