X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fadf435x%2Fpd.py;h=15ec2e5d51d391293409715e01d6ffecaa950c6e;hb=c4aaef2588e962d0bd99f7a88841fcf53956da6b;hp=8f51ee245d43335feca823b9320ba5987ba98aca;hpb=1d4fe1c19c0948fb67b4a91495b126a763ea7adb;p=libsigrokdecode.git

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index 8f51ee2..15ec2e5 100644
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -18,6 +18,7 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import bitpack_lsb
 
 def disabled_enabled(v):
     return ['Disabled', 'Enabled'][v]
@@ -86,55 +87,95 @@ regs = {
 }
 
 ANN_REG = 0
+ANN_WARN = 1
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'adf435x'
     name = 'ADF435x'
     longname = 'Analog Devices ADF4350/1'
     desc = 'Wideband synthesizer with integrated VCO.'
     license = 'gplv3+'
     inputs = ['spi']
-    outputs = ['adf435x']
+    outputs = []
+    tags = ['Clock/timing', 'IC', 'Wireless/RF']
     annotations = (
         # Sent from the host to the chip.
-        ('register', 'Register written to the device'),
+        ('write', 'Register write'),
+        ('warning', "Warnings"),
     )
     annotation_rows = (
-        ('registers', 'Register writes', (ANN_REG,)),
+        ('writes', 'Register writes', (ANN_REG,)),
+        ('warnings', 'Warnings', (ANN_WARN,)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.bits = []
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
+    def putg(self, ss, es, cls, data):
+        self.put(ss, es, self.out_ann, [ cls, data, ])
+
     def decode_bits(self, offset, width):
-        return (sum([(1 << i) if self.bits[offset + i][0] else 0 for i in range(width)]),
-            (self.bits[offset + width - 1][1], self.bits[offset][2]))
+        '''Extract a bit field. Expects LSB input data.'''
+        bits = self.bits[offset:][:width]
+        ss, es = bits[-1][1], bits[0][2]
+        value = bitpack_lsb(bits, 0)
+        return ( value, ( ss, es, ))
 
     def decode_field(self, name, offset, width, parser):
-        val, pos = self.decode_bits(offset, width)
-        self.put(pos[0], pos[1], self.out_ann, [ANN_REG,
-            ['%s: %s' % (name, parser(val) if parser else str(val))]])
-        return val
+        '''Interpret a bit field. Emits an annotation.'''
+        val, ( ss, es, ) = self.decode_bits(offset, width)
+        val = parser(val) if parser else str(val)
+        text = ['%s: %s' % (name, val)]
+        self.putg(ss, es, ANN_REG, text)
+
+    def decode_word(self, ss, es, bits):
+        '''Interpret a 32bit word after accumulation completes.'''
+        # SPI transfer content must be exactly one 32bit word.
+        if len(self.bits) != 32:
+            text = [
+                'Frame error: Bit count: want 32, got %d' % len(self.bits),
+                'Frame error: Bit count',
+                'Frame error',
+            ]
+            self.putg(ss, es, ANN_WARN, text)
+            return
+        # Holding bits in LSB order during interpretation simplifies
+        # bit field extraction. And annotation emitting routines expect
+        # this reverse order of bits' timestamps.
+        self.bits.reverse()
+        # Determine which register was accessed.
+        reg_addr, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
+        text = [
+            'Register: %d' % reg_addr,
+            'Reg: %d' % reg_addr,
+            '[%d]' % reg_addr,
+        ]
+        self.putg(reg_ss, reg_es, ANN_REG, text)
+        # Interpret the register's content (when parsers are available).
+        field_descs = regs.get(reg_addr, None)
+        if not field_descs:
+            return
+        for field_desc in field_descs:
+            self.decode_field(*field_desc)
 
     def decode(self, ss, es, data):
+        ptype, _, _ = data
+
+        if ptype == 'TRANSFER':
+            # Process accumulated bits after completion of a transfer.
+            self.decode_word(ss, es, self.bits)
+            self.bits.clear()
 
-        ptype, data1, data2 = data
-
-        if ptype == 'CS-CHANGE':
-            if data1 == 1:
-                if len(self.bits) == 32:
-                    reg_value, reg_pos = self.decode_bits(0, 3)
-                    self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
-                        ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
-                         '[%d]' % reg_value]])
-                    if reg_value < len(regs):
-                        field_descs = regs[reg_value]
-                        for field_desc in field_descs:
-                            field = self.decode_field(*field_desc)
-                self.bits = []
         if ptype == 'BITS':
-            self.bits = data1 + self.bits
+            _, mosi_bits, miso_bits = data
+            # Accumulate bits in MSB order as they are seen in SPI frames.
+            msb_bits = mosi_bits.copy()
+            msb_bits.reverse()
+            self.bits.extend(msb_bits)