X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoder%2Ftest%2Fparallel%2Ftest.conf;h=a28dd2d5f3f0ca23613b134a3b115e383379a283;hb=1fddbced44d10533e1c15eb237822181084c0a3b;hp=35e9f60a36ec822982fdd1853d5b73decaad55d5;hpb=6b7b93490c7eae859f06b028c629d364075a2016;p=sigrok-test.git

diff --git a/decoder/test/parallel/test.conf b/decoder/test/parallel/test.conf
index 35e9f60..a28dd2d 100644
--- a/decoder/test/parallel/test.conf
+++ b/decoder/test/parallel/test.conf
@@ -1,19 +1,28 @@
 test incremental_8ch_short_noclock
-	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
-	input demo/incremental_8ch_short.sr
+	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
+	input misc/demo/incremental_8ch_short.sr
 	output parallel annotation match incremental_8ch_short_noclock.output
+	output parallel python match incremental_8ch_short_noclock.python
 
 test incremental_8ch_short_clock
 	protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
-	input demo/incremental_8ch_short.sr
+	input misc/demo/incremental_8ch_short.sr
 	output parallel annotation match incremental_8ch_short_clock.output
+	output parallel python match incremental_8ch_short_clock.python
 
 test incremental_8ch_long_noclock
-	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
-	input demo/incremental_8ch_long.sr
+	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
+	input misc/demo/incremental_8ch_long.sr
 	output parallel annotation match incremental_8ch_long_noclock.output
+	output parallel python match incremental_8ch_long_noclock.python
 
 test incremental_8ch_long_clock
 	protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
-	input demo/incremental_8ch_long.sr
+	input misc/demo/incremental_8ch_long.sr
 	output parallel annotation match incremental_8ch_long_clock.output
+	output parallel python match incremental_8ch_long_clock.python
+
+test hd44780_word_demux
+	protocol-decoder parallel channel clk=3 channel d0=4 channel d1=5 channel d2=6 channel d3=7 option clock_edge=falling option wordsize=2 option endianness=big
+	input hd44780/hd44780-reset-init-hello.sr
+	output parallel annotation match hd44780_word_demux.output