X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoder%2Ftest%2Fparallel%2Ftest.conf;h=1e751a40754e172bc8da4d453d43e02f11d38e9d;hb=f47a7a3b76716f1b83fe3d06ae27e8032736eb5c;hp=e894ee2738d1b9cd2459e8b7c5557dc0f17574af;hpb=67115888c5dcb9d4987acd6d2daf58778ddf74b4;p=sigrok-test.git

diff --git a/decoder/test/parallel/test.conf b/decoder/test/parallel/test.conf
index e894ee2..1e751a4 100644
--- a/decoder/test/parallel/test.conf
+++ b/decoder/test/parallel/test.conf
@@ -1,19 +1,34 @@
 test incremental_8ch_short_noclock
-	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
+	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
 	input misc/demo/incremental_8ch_short.sr
 	output parallel annotation match incremental_8ch_short_noclock.output
+	output parallel python match incremental_8ch_short_noclock.python
 
 test incremental_8ch_short_clock
 	protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
 	input misc/demo/incremental_8ch_short.sr
 	output parallel annotation match incremental_8ch_short_clock.output
+	output parallel python match incremental_8ch_short_clock.python
 
 test incremental_8ch_long_noclock
-	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
+	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
 	input misc/demo/incremental_8ch_long.sr
 	output parallel annotation match incremental_8ch_long_noclock.output
+	output parallel python match incremental_8ch_long_noclock.python
 
 test incremental_8ch_long_clock
 	protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
 	input misc/demo/incremental_8ch_long.sr
 	output parallel annotation match incremental_8ch_long_clock.output
+	output parallel python match incremental_8ch_long_clock.python
+
+test hd44780_word_demux
+	protocol-decoder parallel channel clk=3 channel d0=4 channel d1=5 channel d2=6 channel d3=7 option clock_edge=falling option wordsize=2 option endianness=big
+	input display/hd44780/hd44780-reset-init-hello.sr
+	output parallel annotation match hd44780_word_demux.output
+
+test spi_sqi_four_lines_one_xfer
+	protocol-decoder parallel channel clk=2 channel d0=4 channel d1=5 channel d2=6 channel d3=7 channel rst=3 option clock_edge=rising option reset_polarity=high-active option wordsize=2 option endianness=big
+	input spi/sqi/sqi-four-data-lines-one-transfer.sr
+	output parallel annotation match spi_sqi_four_lines_three_transfers.output
+	output parallel python match spi_sqi_four_lines_one_xfer.python