X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=Makefile.am;h=7b67a9a5e4a408394427cd65aef57789e25dd384;hb=3250d8c7e05f2d6a3ffbdf2499af8a13fa99fe39;hp=e81ead05c931479910f9b615a9d92c3bc948cfac;hpb=90bd7656401dd178756597d133581e08615093d7;p=libsigrok.git diff --git a/Makefile.am b/Makefile.am index e81ead05..7b67a9a5 100644 --- a/Makefile.am +++ b/Makefile.am @@ -20,7 +20,7 @@ ACLOCAL_AMFLAGS = -I autostuff -AM_CPPFLAGS = -Isrc -DFIRMWARE_DIR='"$(FIRMWARE_DIR)"' +AM_CPPFLAGS = -I$(srcdir)/src -DFIRMWARE_DIR='"$(FIRMWARE_DIR)"' lib_LTLIBRARIES = libsigrok.la @@ -43,10 +43,10 @@ libsigrok_la_SOURCES = \ # Input modules libsigrok_la_SOURCES += \ + src/input/input.c \ src/input/binary.c \ src/input/chronovu_la8.c \ src/input/csv.c \ - src/input/input.c \ src/input/vcd.c \ src/input/wav.c @@ -59,9 +59,11 @@ libsigrok_la_SOURCES += \ src/output/binary.c \ src/output/csv.c \ src/output/chronovu_la8.c \ + src/output/wav.c \ src/output/gnuplot.c \ src/output/hex.c \ src/output/ols.c \ + src/output/srzip.c \ src/output/vcd.c # SCPI support @@ -90,6 +92,10 @@ if NEED_VISA libsigrok_la_SOURCES += \ src/scpi/scpi_visa.c endif +if NEED_GPIB +libsigrok_la_SOURCES += \ + src/scpi/scpi_libgpib.c +endif # Hardware (DMM chip parsers) libsigrok_la_SOURCES += \ @@ -98,7 +104,15 @@ libsigrok_la_SOURCES += \ src/dmm/fs9922.c \ src/dmm/m2110.c \ src/dmm/metex14.c \ - src/dmm/rs9lcd.c + src/dmm/rs9lcd.c \ + src/dmm/bm25x.c \ + src/dmm/ut71x.c + +# Hardware (LCR chip parsers) +if HW_DEREE_DE5000 +libsigrok_la_SOURCES += \ + src/lcr/es51919.c +endif # Hardware drivers if HW_AGILENT_DMM @@ -178,6 +192,10 @@ if HW_DEMO libsigrok_la_SOURCES += \ src/hardware/demo/demo.c endif +if HW_DEREE_DE5000 +libsigrok_la_SOURCES += \ + src/hardware/deree-de5000/api.c +endif if HW_FLUKE_DMM libsigrok_la_SOURCES += \ src/hardware/fluke-dmm/fluke-dmm.h \ @@ -262,6 +280,12 @@ libsigrok_la_SOURCES += \ src/hardware/openbench-logic-sniffer/protocol.c \ src/hardware/openbench-logic-sniffer/api.c endif +if HW_PIPISTRELLO_OLS +libsigrok_la_SOURCES += \ + src/hardware/pipistrello-ols/protocol.h \ + src/hardware/pipistrello-ols/protocol.c \ + src/hardware/pipistrello-ols/api.c +endif if HW_RIGOL_DS libsigrok_la_SOURCES += \ src/hardware/rigol-ds/protocol.h \ @@ -274,6 +298,13 @@ libsigrok_la_SOURCES += \ src/hardware/saleae-logic16/protocol.c \ src/hardware/saleae-logic16/api.c endif +if HW_SCPI_PPS +libsigrok_la_SOURCES += \ + src/hardware/scpi-pps/protocol.h \ + src/hardware/scpi-pps/protocol.c \ + src/hardware/scpi-pps/profiles.c \ + src/hardware/scpi-pps/api.c +endif if HW_SERIAL_DMM libsigrok_la_SOURCES += \ src/hardware/serial-dmm/protocol.h \ @@ -324,6 +355,14 @@ libsigrok_la_SOURCES += \ src/hardware/victor-dmm/protocol.c \ src/hardware/victor-dmm/api.c endif +if HW_YOKOGAWA_DLM +libsigrok_la_SOURCES += \ + src/hardware/yokogawa-dlm/protocol.h \ + src/hardware/yokogawa-dlm/protocol.c \ + src/hardware/yokogawa-dlm/protocol_wrappers.h \ + src/hardware/yokogawa-dlm/protocol_wrappers.c \ + src/hardware/yokogawa-dlm/api.c +endif if HW_ZEROPLUS_LOGIC_CUBE libsigrok_la_SOURCES += \ src/hardware/zeroplus-logic-cube/analyzer.c \ @@ -376,9 +415,11 @@ tests_check_main_SOURCES = \ tests/check_input_all.c \ tests/check_input_binary.c \ tests/check_output_all.c \ + tests/check_session.c \ tests/check_strutil.c \ tests/check_version.c \ - tests/check_driver_all.c + tests/check_driver_all.c \ + tests/check_device.c tests_check_main_CFLAGS = @check_CFLAGS@ @@ -406,23 +447,24 @@ library_include_HEADERS += \ pkgconfig_DATA += bindings/cxx/libsigrokxx.pc -bindings/cxx/libsigrok.xml: include/libsigrok/libsigrok.h - $(AM_V_GEN)gccxml $(CFLAGS) -DGLIB_DISABLE_DEPRECATION_WARNINGS $< -fxml=$@ +doxy/xml/index.xml: include/libsigrok/libsigrok.h + $(AM_V_GEN)cd $(srcdir) && BUILDDIR=$(abs_builddir)/ doxygen Doxyfile 2>/dev/null bindings/cxx/enums.cpp: bindings/cxx/enums.timestamp bindings/cxx/include/libsigrok/enums.hpp: bindings/cxx/enums.timestamp -bindings/cxx/enums.timestamp: bindings/cxx/enums.py bindings/cxx/libsigrok.xml \ +bindings/cxx/enums.timestamp: bindings/cxx/enums.py doxy/xml/index.xml \ bindings/cxx/ConfigKey_methods.cpp bindings/cxx/QuantityFlag_methods.cpp - $(AM_V_GEN)python $< + $(AM_V_GEN)$(PYTHON) $< doxy/xml/index.xml $(AM_V_at)touch $@ bindings/cxx/classes.lo: bindings/cxx/classes.cpp bindings/cxx/enums.cpp \ $(library_include_HEADERS) cxx-clean: - rm -f bindings/cxx/libsigrok.xml + rm -rf doxy/ + rm -rf bindings/cxx/doxy/ rm -f bindings/cxx/enums.cpp rm -f bindings/cxx/include/libsigrok/enums.hpp rm -f bindings/cxx/enums.timestamp @@ -431,29 +473,44 @@ CLEAN_EXTRA += cxx-clean endif +CPPXMLDOC = bindings/cxx/doxy/xml/index.xml + +$(CPPXMLDOC): bindings/cxx/include/libsigrok/libsigrok.hpp \ + bindings/cxx/enums.timestamp + $(AM_V_GEN)cd $(srcdir)/bindings/cxx && BUILDDIR=$(abs_builddir)/bindings/cxx/ doxygen Doxyfile 2>/dev/null + if BINDINGS_PYTHON PDIR = bindings/python +PDOC = bindings/python/sigrok/core/doc.i + +$(PDOC): bindings/swig/doc.py $(CPPXMLDOC) + $(AM_V_at)test -d $(PDIR)/sigrok/core || mkdir -p $(PDIR)/sigrok/core + $(AM_V_GEN)$(PYTHON) $< python $(CPPXMLDOC) > $@ python-build: $(PDIR)/timestamp python-quietclean: - $(AM_V_at)cd $(PDIR) && python setup.py --quiet clean --all 3>&1 1>&2 2>&3 \ + $(AM_V_at)cd $(PDIR) && $(PYTHON) $(abs_srcdir)/$(PDIR)/setup.py --quiet clean --all 3>&1 1>&2 2>&3 \ | grep -v "can.t clean it"; true $(PDIR)/timestamp: bindings/cxx/libsigrokxx.la $(PDIR)/sigrok/core/classes.i \ - bindings/swig/classes.i $(library_include_HEADERS) + bindings/swig/classes.i $(PDOC) $(library_include_HEADERS) $(AM_V_at)$(MAKE) python-quietclean - $(AM_V_GEN)cd $(PDIR) && python setup.py --quiet build 3>&1 1>&2 2>&3 \ + $(AM_V_GEN)cd $(PDIR) && $(PYTHON) $(abs_srcdir)/$(PDIR)/setup.py --quiet build 3>&1 1>&2 2>&3 \ | grep -v "command line option.*Wstrict-prototypes"; true $(AM_V_at)touch $(PDIR)/timestamp python-install: - cd $(PDIR) && python setup.py --quiet install --prefix $(prefix) + cd $(PDIR) && $(PYTHON) $(abs_srcdir)/$(PDIR)/setup.py --quiet install --prefix $(prefix) python-clean: $(AM_V_at)$(MAKE) python-quietclean $(AM_V_at)rm -f $(PDIR)/timestamp + $(AM_V_at)rm -rf $(PDIR)/doxy/ + +python-doc: + $(AM_V_at)cd $(srcdir)/$(PDIR) && BUILDDIR=$(abs_builddir)/$(PDIR)/ doxygen Doxyfile 2>/dev/null BUILD_EXTRA += python-build INSTALL_EXTRA += python-install @@ -467,24 +524,30 @@ JDIR = bindings/java JPKG = org/sigrok/core JCLS = $(JDIR)/$(JPKG)/classes JINT = $(JDIR)/$(JPKG)/interfaces -JSRC = $(JCLS)/*.java $(JINT)/*.java +JSRC = $(JCLS)/*.java $(srcdir)/$(JINT)/*.java JSWG = $(JCLS)/classes.i +JDOC = $(JCLS)/doc.i JCXX = $(JCLS)/classes_wrap.cxx JLIB = $(JDIR)/libsigrok_java_core_classes.so JJAR = $(JDIR)/sigrok-core.jar java-build: $(JJAR) $(JLIB) -$(JCXX): $(JSWG) bindings/swig/classes.i $(library_include_HEADERS) +$(JDOC): bindings/swig/doc.py $(CPPXMLDOC) + $(AM_V_at)test -d $(JCLS) || mkdir -p $(JCLS) + $(AM_V_GEN)python $< java $(CPPXMLDOC) > $@ + +$(JCXX): $(JSWG) $(JDOC) bindings/swig/classes.i $(library_include_HEADERS) + $(AM_V_at)make java-clean $(AM_V_GEN)swig -c++ -java -package org.sigrok.core.classes \ - -Iinclude -Ibindings/cxx/include -outdir $(JCLS) $(JSWG) + -I$(srcdir)/include -I$(srcdir)/bindings/cxx/include -I$(srcdir) -I$(JCLS) -Ibindings/cxx/include -outdir $(JCLS) -o $@ $< $(JJAR): $(JCXX) - $(AM_V_GEN)$(JAVAC) -sourcepath $(JDIR) $(JSRC) + $(AM_V_GEN)$(JAVAC) -sourcepath $(JDIR) -d $(JDIR) $(JSRC) $(AM_V_at)jar cf $(JJAR) -C $(JDIR) $(JPKG) $(JLIB): $(JCXX) bindings/cxx/libsigrokxx.la $(library_include_HEADERS) - $(AM_V_GEN)$(CXX) $(CXXFLAGS) -L.libs -Lbindings/cxx/.libs \ + $(AM_V_GEN)$(CXXCOMPILE) -L.libs -Lbindings/cxx/.libs \ -fno-strict-aliasing -fPIC -shared $(JCLS)/classes_wrap.cxx \ -lsigrokxx -o $(JLIB) @@ -495,12 +558,16 @@ java-install: $(INSTALL) $(JJAR) -t $(datadir)/java java-clean: - rm -f $(JCXX) - rm -f $(JCLS)/*.java - rm -f $(JCLS)/*.class - rm -f $(JINT)/*.class - rm -f $(JJAR) - rm -f $(JLIB) + $(AM_V_at)rm -f $(JCXX) + $(AM_V_at)rm -f $(JCLS)/*.java + $(AM_V_at)rm -f $(JCLS)/*.class + $(AM_V_at)rm -f $(JINT)/*.class + $(AM_V_at)rm -f $(JJAR) + $(AM_V_at)rm -f $(JLIB) + $(AM_V_at)rm -rf $(JDIR)/doxy/ + +java-doc: + $(AM_V_at)cd $(srcdir)/$(JDIR) && BUILDDIR=$(abs_builddir)/$(JDIR)/ doxygen Doxyfile 2>/dev/null BUILD_EXTRA += java-build INSTALL_EXTRA += java-install