X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=Makefile.am;h=26319566301960d243f5437c0fef1fc6569fe5f4;hb=25f94dfebced0db7b0c0c403a1c90c517017fca5;hp=78ae7c7d50d4c3be5d2a3bd3f25ed77d7bc889fd;hpb=0e1a7fe91a9132ad586337bdd29d93eff4344edd;p=libsigrok.git

diff --git a/Makefile.am b/Makefile.am
index 78ae7c7d..26319566 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -43,10 +43,10 @@ libsigrok_la_SOURCES = \
 
 # Input modules
 libsigrok_la_SOURCES += \
+	src/input/input.c \
 	src/input/binary.c \
 	src/input/chronovu_la8.c \
 	src/input/csv.c \
-	src/input/input.c \
 	src/input/vcd.c \
 	src/input/wav.c
 
@@ -91,6 +91,10 @@ if NEED_VISA
 libsigrok_la_SOURCES += \
 	src/scpi/scpi_visa.c
 endif
+if NEED_GPIB
+libsigrok_la_SOURCES += \
+	src/scpi/scpi_libgpib.c
+endif
 
 # Hardware (DMM chip parsers)
 libsigrok_la_SOURCES += \
@@ -264,6 +268,12 @@ libsigrok_la_SOURCES += \
 	src/hardware/openbench-logic-sniffer/protocol.c \
 	src/hardware/openbench-logic-sniffer/api.c
 endif
+if HW_PIPISTRELLO_OLS
+libsigrok_la_SOURCES += \
+	src/hardware/pipistrello-ols/protocol.h \
+	src/hardware/pipistrello-ols/protocol.c \
+	src/hardware/pipistrello-ols/api.c
+endif
 if HW_RIGOL_DS
 libsigrok_la_SOURCES += \
 	src/hardware/rigol-ds/protocol.h \
@@ -276,6 +286,13 @@ libsigrok_la_SOURCES += \
 	src/hardware/saleae-logic16/protocol.c \
 	src/hardware/saleae-logic16/api.c
 endif
+if HW_SCPI_PPS
+libsigrok_la_SOURCES += \
+	src/hardware/scpi-pps/protocol.h \
+	src/hardware/scpi-pps/protocol.c \
+	src/hardware/scpi-pps/profiles.c \
+	src/hardware/scpi-pps/api.c
+endif
 if HW_SERIAL_DMM
 libsigrok_la_SOURCES += \
 	src/hardware/serial-dmm/protocol.h \
@@ -326,6 +343,14 @@ libsigrok_la_SOURCES += \
 	src/hardware/victor-dmm/protocol.c \
 	src/hardware/victor-dmm/api.c
 endif
+if HW_YOKOGAWA_DLM
+libsigrok_la_SOURCES += \
+	src/hardware/yokogawa-dlm/protocol.h \
+	src/hardware/yokogawa-dlm/protocol.c \
+	src/hardware/yokogawa-dlm/protocol_wrappers.h \
+	src/hardware/yokogawa-dlm/protocol_wrappers.c \
+	src/hardware/yokogawa-dlm/api.c
+endif
 if HW_ZEROPLUS_LOGIC_CUBE
 libsigrok_la_SOURCES += \
 	src/hardware/zeroplus-logic-cube/analyzer.c \
@@ -500,6 +525,7 @@ $(JDOC): bindings/swig/doc.py $(CPPXMLDOC)
 	$(AM_V_GEN)python $< java $(CPPXMLDOC) > $@
 
 $(JCXX): $(JSWG) $(JDOC) bindings/swig/classes.i $(library_include_HEADERS)
+	$(AM_V_at)make java-clean
 	$(AM_V_GEN)swig -c++ -java -package org.sigrok.core.classes \
 		-I$(srcdir)/include -I$(srcdir)/bindings/cxx/include -I$(srcdir) -I$(JCLS) -Ibindings/cxx/include -outdir $(JCLS) -o $@ $<
 
@@ -508,7 +534,7 @@ $(JJAR): $(JCXX)
 	$(AM_V_at)jar cf $(JJAR) -C $(JDIR) $(JPKG)
 
 $(JLIB): $(JCXX) bindings/cxx/libsigrokxx.la $(library_include_HEADERS)
-	$(AM_V_GEN)$(CXX) $(CXXFLAGS) -L.libs -Lbindings/cxx/.libs \
+	$(AM_V_GEN)$(CXXCOMPILE) -L.libs -Lbindings/cxx/.libs \
 		-fno-strict-aliasing -fPIC -shared $(JCLS)/classes_wrap.cxx \
 		-lsigrokxx -o $(JLIB)
 
@@ -519,13 +545,13 @@ java-install:
 	$(INSTALL) $(JJAR) -t $(datadir)/java
 
 java-clean:
-	rm -f $(JCXX)
-	rm -f $(JCLS)/*.java
-	rm -f $(JCLS)/*.class
-	rm -f $(JINT)/*.class
-	rm -f $(JJAR)
-	rm -f $(JLIB)
-	rm -rf $(JDIR)/doxy/
+	$(AM_V_at)rm -f $(JCXX)
+	$(AM_V_at)rm -f $(JCLS)/*.java
+	$(AM_V_at)rm -f $(JCLS)/*.class
+	$(AM_V_at)rm -f $(JINT)/*.class
+	$(AM_V_at)rm -f $(JJAR)
+	$(AM_V_at)rm -f $(JLIB)
+	$(AM_V_at)rm -rf $(JDIR)/doxy/
 
 java-doc:
 	$(AM_V_at)cd $(srcdir)/$(JDIR) && BUILDDIR=$(abs_builddir)/$(JDIR)/ doxygen Doxyfile 2>/dev/null