X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.h;h=0cadd359517fc043f3fd9c4f35acd06b671de1be;hb=d586a7f4bd0d83a1e432d5ca1ee63af94bdb4e13;hp=00979a305cedd825bd29fcad3cba5beeb2030369;hpb=5a971f66a37df7c4dbe7799b3c7fc7eb30055a61;p=libsigrok.git

diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h
index 00979a30..0cadd359 100644
--- a/src/hardware/saleae-logic16/protocol.h
+++ b/src/hardware/saleae-logic16/protocol.h
@@ -37,6 +37,7 @@ enum voltage_range {
 
 enum fpga_variant {
 	FPGA_VARIANT_ORIGINAL,
+	FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM,
 	FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 
@@ -90,6 +91,10 @@ struct dev_context {
 	unsigned int num_transfers;
 	struct libusb_transfer **transfers;
 	struct sr_context *ctx;
+
+	const uint8_t *fpga_register_map;
+	const uint8_t *fpga_status_control_bit_map;
+	const uint8_t *fpga_mode_bit_map;
 };
 
 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
@@ -97,6 +102,6 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi);
-SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer);
+SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer);
 
 #endif