X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.c;h=3db8a82f0b8577b9bf580324b9f2a96598dcb013;hb=55462b8ba9f48931de9b9a7bfbc182a1d113b3b5;hp=ac53cee88866553471003c6b011de0313f8604db;hpb=6f479a0a72492b2a28344de04776733b19fdbaa9;p=libsigrok.git diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c index ac53cee8..3db8a82f 100644 --- a/src/hardware/saleae-logic16/protocol.c +++ b/src/hardware/saleae-logic16/protocol.c @@ -19,8 +19,6 @@ * along with this program. If not, see . */ -#include "protocol.h" - #include #include #include @@ -30,6 +28,7 @@ #include #include "libsigrok.h" #include "libsigrok-internal.h" +#include "protocol.h" #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream" #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream" @@ -107,7 +106,7 @@ static int do_ep1_command(const struct sr_dev_inst *sdi, usb = sdi->conn; if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || - command == NULL || (reply_len > 0 && reply == NULL)) + !command || (reply_len > 0 && !reply)) return SR_ERR_ARG; encrypt(buf, command, cmd_len); @@ -165,7 +164,7 @@ static int upload_led_table(const struct sr_dev_inst *sdi, uint8_t chunk, command[64]; int ret; - if (cnt < 1 || cnt + offset > 64 || table == NULL) + if (cnt < 1 || cnt + offset > 64 || !table) return SR_ERR_ARG; while (cnt > 0) { @@ -351,7 +350,7 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, } sr_info("Uploading FPGA bitstream at %s.", filename); - if ((fw = g_fopen(filename, "rb")) == NULL) { + if (!(fw = g_fopen(filename, "rb"))) { sr_err("Unable to open bitstream file %s for reading: %s.", filename, strerror(errno)); return SR_ERR; @@ -470,8 +469,8 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, reg1 &= ~0x20; if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) { - sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1); - return SR_ERR; + sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08. " + "Proceeding anyway.", reg1); } if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) @@ -499,17 +498,16 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, return ret; if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) { - sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1); - return SR_ERR; + sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. " + "Proceeding anyway.", reg1); } if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK) return ret; if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) { - sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.", - reg10, clock_select); - return SR_ERR; + sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " + "Proceeding anyway.", reg10, clock_select); } return SR_OK; @@ -704,7 +702,7 @@ static size_t convert_sample_data(struct dev_context *devc, return ret; } -SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer) +SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer) { gboolean packet_has_error = FALSE; struct sr_datafeed_packet packet; @@ -713,6 +711,7 @@ SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer) struct dev_context *devc; size_t new_samples, num_samples; int trigger_offset; + int pre_trigger_samples; sdi = transfer->user_data; devc = sdi->priv; @@ -726,8 +725,8 @@ SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer) return; } - sr_info("receive_transfer(): status %d received %d bytes.", - transfer->status, transfer->actual_length); + sr_info("receive_transfer(): status %s received %d bytes.", + libusb_error_name(transfer->status), transfer->actual_length); switch (transfer->status) { case LIBUSB_TRANSFER_NO_DEVICE: @@ -785,8 +784,9 @@ SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer) devc->sent_samples += new_samples; } else { trigger_offset = soft_trigger_logic_check(devc->stl, - devc->convbuffer, new_samples * 2); + devc->convbuffer, new_samples * 2, &pre_trigger_samples); if (trigger_offset > -1) { + devc->sent_samples += pre_trigger_samples; packet.type = SR_DF_LOGIC; packet.payload = &logic; num_samples = new_samples - trigger_offset;