X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fz80%2Fpd.py;h=cdbebebf27e2c2f0ceb8e02beab7afc5f00d538b;hb=7b0f3c78c5cda82b900937f3be2e08b063b84f3c;hp=299a20ec72496cc8ee27eb7b965ab0d85ff8d72d;hpb=6a15597a7b3f901b566b7bfc8c484a14e0fb6a11;p=libsigrokdecode.git

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index 299a20e..cdbebeb 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -64,14 +64,15 @@ def signed_byte(byte):
     return byte if byte < 128 else byte - 256
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 3
     id       = 'z80'
     name     = 'Z80'
     longname = 'Zilog Z80 CPU'
     desc     = 'Zilog Z80 microprocessor disassembly.'
     license  = 'gplv3+'
     inputs   = ['logic']
-    outputs  = ['z80']
+    outputs  = []
+    tags     = ['Retro computing']
     channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
@@ -92,15 +93,15 @@ class Decoder(srd.Decoder):
         } for i in range(16)
     )
     annotations = (
-        ('addr',  'Memory or I/O address'),
+        ('addr', 'Memory or I/O address'),
         ('memrd', 'Byte read from memory'),
         ('memwr', 'Byte written to memory'),
-        ('iord',  'Byte read from I/O port'),
-        ('iowr',  'Byte written to I/O port'),
+        ('iord', 'Byte read from I/O port'),
+        ('iowr', 'Byte written to I/O port'),
         ('instr', 'Z80 CPU instruction'),
-        ('rop',   'Value of input operand'),
-        ('wop',   'Value of output operand'),
-        ('warn',  'Warning message'),
+        ('rop', 'Value of input operand'),
+        ('wop', 'Value of output operand'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('addrbus', 'Address bus', (Ann.ADDR,)),
@@ -110,7 +111,10 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (Ann.WARN,))
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.prev_cycle = Cycle.NONE
         self.op_state   = self.state_IDLE
 
@@ -129,8 +133,10 @@ class Decoder(srd.Decoder):
         self.op_state   = self.state_IDLE
         self.instr_len  = 0
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
+    def decode(self):
+        while True:
+            # TODO: Come up with more appropriate self.wait() conditions.
+            pins = self.wait()
             cycle = Cycle.NONE
             if pins[Pin.MREQ] != 1: # default to asserted
                 if pins[Pin.RD] == 0: