X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fuart%2Fpd.py;h=d59c6c33fb3fd5738fc84479ae32df99d7c9fd89;hb=1c49e875623918f8893308307f487a1f551daec4;hp=da5e3033b3023cce80f8416ac96b580815d80eb0;hpb=21cda9512f29947617da45822ab524b1f76f56c1;p=libsigrokdecode.git

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index da5e303..d59c6c3 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -28,9 +28,10 @@ Packet:
 
 This is the list of <ptype>s and their respective <pdata> values:
  - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
- - 'DATA': The data is the (integer) value of the UART data. Valid values
-   range from 0 to 512 (as the data can be up to 9 bits in size).
- - 'DATABITS': List of data bits and their ss/es numbers.
+ - 'DATA': This is always a tuple containing two items:
+   - 1st item: the (integer) value of the UART data. Valid values
+     range from 0 to 512 (as the data can be up to 9 bits in size).
+   - 2nd item: the list of individual data bits and their ss/es numbers.
  - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
  - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
  - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
@@ -66,12 +67,13 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
         return (ones % 2) == 1
     elif parity_type == 'even':
         return (ones % 2) == 0
-    else:
-        raise Exception('Invalid parity type: %d' % parity_type)
 
 class SamplerateError(Exception):
     pass
 
+class ChannelError(Exception):
+    pass
+
 class Decoder(srd.Decoder):
     api_version = 2
     id = 'uart'
@@ -101,7 +103,10 @@ class Decoder(srd.Decoder):
             'values': ('lsb-first', 'msb-first')},
         {'id': 'format', 'desc': 'Data format', 'default': 'ascii',
             'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
-        # TODO: Options to invert the signal(s).
+        {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no',
+            'values': ('yes', 'no')},
+        {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no',
+            'values': ('yes', 'no')},
     )
     annotations = (
         ('rx-data', 'RX data'),
@@ -175,7 +180,7 @@ class Decoder(srd.Decoder):
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
-            self.samplerate = value;
+            self.samplerate = value
             # The width of one UART bit in number of samples.
             self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
 
@@ -242,12 +247,9 @@ class Decoder(srd.Decoder):
             self.databyte[rxtx] >>= 1
             self.databyte[rxtx] |= \
                 (signal << (self.options['num_data_bits'] - 1))
-        elif self.options['bit_order'] == 'msb-first':
+        else:
             self.databyte[rxtx] <<= 1
             self.databyte[rxtx] |= (signal << 0)
-        else:
-            raise Exception('Invalid bit order value: %s',
-                            self.options['bit_order'])
 
         self.putg([rxtx + 12, ['%d' % signal]])
 
@@ -262,8 +264,8 @@ class Decoder(srd.Decoder):
 
         self.state[rxtx] = 'GET PARITY BIT'
 
-        self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]])
-        self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]])
+        self.putpx(rxtx, ['DATA', rxtx,
+            (self.databyte[rxtx], self.databits[rxtx])])
 
         b, f = self.databyte[rxtx], self.options['format']
         if f == 'ascii':
@@ -277,8 +279,6 @@ class Decoder(srd.Decoder):
             self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
         elif f == 'bin':
             self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
-        else:
-            raise Exception('Invalid data format option: %s' % f)
 
         self.putbin(rxtx, (rxtx, bytes([b])))
         self.putbin(rxtx, (2, bytes([b])))
@@ -340,10 +340,15 @@ class Decoder(srd.Decoder):
             #     continue
             self.oldpins, (rx, tx) = pins, pins
 
+            if self.options['invert_rx'] == 'yes':
+                rx = not rx
+            if self.options['invert_tx'] == 'yes':
+                tx = not tx
+
             # Either RX or TX (but not both) can be omitted.
             has_pin = [rx in (0, 1), tx in (0, 1)]
             if has_pin == [False, False]:
-                raise Exception('Either TX or RX (or both) pins required.')
+                raise ChannelError('Either TX or RX (or both) pins required.')
 
             # State machine.
             for rxtx in (RX, TX):
@@ -366,4 +371,3 @@ class Decoder(srd.Decoder):
 
                 # Save current RX/TX values for the next round.
                 self.oldbit[rxtx] = signal
-