X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fsdcard_spi%2Fpd.py;h=1e02756987b582e139feadd28cc19b4abac08584;hb=8f461b610c0887db253dc289471beeb1da6f08ea;hp=6b5486d32b492ca425831e20717b9b9e1f476374;hpb=984e3e3d3202e531c723b2e945529785a0f02ace;p=libsigrokdecode.git

diff --git a/decoders/sdcard_spi/pd.py b/decoders/sdcard_spi/pd.py
index 6b5486d..1e02756 100644
--- a/decoders/sdcard_spi/pd.py
+++ b/decoders/sdcard_spi/pd.py
@@ -227,7 +227,7 @@ class Decoder(srd.Decoder):
         self.state = 'GET RESPONSE R1'
 
     def handle_cmd24(self):
-        # CMD24: WRITE_SINGLE_BLOCK
+        # CMD24: WRITE_BLOCK
         self.putc(24, 'Write a block to address 0x%04x' % self.arg)
         self.is_cmd24 = True
         self.state = 'GET RESPONSE R1'
@@ -378,24 +378,34 @@ class Decoder(srd.Decoder):
             self.read_buf = []
             self.state = 'DATA RESPONSE'
         elif mosi == 0xfe:
-            self.put(self.ss, self.es, self.out_ann, [24, ['Data Start Token']])
+            self.put(self.ss, self.es, self.out_ann, [24, ['Start Block']])
             self.cmd24_start_token_found = True
 
     def handle_data_response(self, miso):
+        # Data Response token (1 byte).
+        #
+        # Format:
+        #  - Bits[7:5]: Don't care.
+        #  - Bits[4:4]: Always 0.
+        #  - Bits[3:1]: Status.
+        #    - 010: Data accepted.
+        #    - 101: Data rejected due to a CRC error.
+        #    - 110: Data rejected due to a write error.
+        #  - Bits[0:0]: Always 1.
         miso &= 0x1f
         if miso & 0x11 != 0x01:
             # This is not the byte we are waiting for.
             # Should we return to IDLE here?
             return
-        self.put(self.miso_bits[7][1], self.miso_bits[5][2], self.out_ann, [134, ['don\'t care']])
-        self.put(self.miso_bits[4][1], self.miso_bits[4][2], self.out_ann, [134, ['0']])
+        self.put(self.miso_bits[7][1], self.miso_bits[5][2], self.out_ann, [134, ['Don\'t care']])
+        self.put(self.miso_bits[4][1], self.miso_bits[4][2], self.out_ann, [134, ['Always 0']])
         if miso == 0x05:
             self.put(self.miso_bits[3][1], self.miso_bits[1][2], self.out_ann, [134, ['Data accepted']])
         elif miso == 0x0b:
             self.put(self.miso_bits[3][1], self.miso_bits[1][2], self.out_ann, [134, ['Data rejected (CRC error)']])
         elif miso == 0x0d:
             self.put(self.miso_bits[3][1], self.miso_bits[1][2], self.out_ann, [134, ['Data rejected (write error)']])
-        self.put(self.miso_bits[0][1], self.miso_bits[0][2], self.out_ann, [134, ['1']])
+        self.put(self.miso_bits[0][1], self.miso_bits[0][2], self.out_ann, [134, ['Always 1']])
         ann_class = None
         if self.is_cmd24:
             ann_class = 24