X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fnunchuk%2Fnunchuk.py;h=a3fdf779d7b83d51e4d4d55c4193db19c5f32e24;hb=d628cdb521159d600cb19a3cd04eec28e07d9220;hp=b274f4ad00578ab08fc9eb616ae23b9471df4869;hpb=739f1b7310b5b6926dfd8e9991bcb2fe057eca5d;p=libsigrokdecode.git diff --git a/decoders/nunchuk/nunchuk.py b/decoders/nunchuk/nunchuk.py index b274f4a..a3fdf77 100644 --- a/decoders/nunchuk/nunchuk.py +++ b/decoders/nunchuk/nunchuk.py @@ -41,7 +41,7 @@ class Decoder(srd.Decoder): def __init__(self, **kwargs): self.state = 'IDLE' - self.sx = self.sy = self.ax = self.ay = self.az = self.bz = self.bc = 0 + self.sx = self.sy = self.ax = self.ay = self.az = self.bz = self.bc = -1 self.databytecount = 0 self.reg = 0x00 @@ -109,6 +109,28 @@ class Decoder(srd.Decoder): self.putx([0, ['Accelerometer Z value bits[1:0]: 0x%x' % az_rest]]) self.putx([1, ['AZ[1:0]: 0x%x' % az_rest]]) + def output_full_block_if_possible(self): + # For now, only output summary annotation if all values are available. + t = (self.sx, self.sy, self.ax, self.ay, self.az, self.bz, self.bc) + if -1 in t: + return + + s = 'Analog stick X position: 0x%02x\n' % self.sx + s += 'Analog stick Y position: 0x%02x\n' % self.sy + s += 'Z button: %spressed\n' % ('' if (self.bz == 0) else 'not ') + s += 'C button: %spressed\n' % ('' if (self.bc == 0) else 'not ') + s += 'Accelerometer X value: 0x%03x\n' % self.ax + s += 'Accelerometer Y value: 0x%03x\n' % self.ay + s += 'Accelerometer Z value: 0x%03x\n' % self.az + self.put(self.block_start_sample, self.block_end_sample, + self.out_ann, [0, [s]]) + + s = 'SX = 0x%02x, SY = 0x%02x, AX = 0x%02x, AY = 0x%02x, ' \ + 'AZ = 0x%02x, BZ = 0x%02x, BC = 0x%02x' % (self.sx, \ + self.sy, self.ax, self.ay, self.az, self.bz, self.bc) + self.put(self.block_start_sample, self.block_end_sample, + self.out_ann, [1, [s]]) + def decode(self, ss, es, data): cmd, databyte = data @@ -134,17 +156,9 @@ class Decoder(srd.Decoder): self.reg += 1 elif cmd == 'STOP': self.block_end_sample = es - - # TODO: Only works if host reads _all_ regs (0x00 - 0x05). - d = 'SX = 0x%02x, SY = 0x%02x, AX = 0x%02x, AY = 0x%02x, ' \ - 'AZ = 0x%02x, BZ = 0x%02x, BC = 0x%02x' % (self.sx, \ - self.sy, self.ax, self.ay, self.az, self.bz, self.bc) - self.put(self.block_start_sample, self.block_end_sample, - self.out_ann, [0, [d]]) - - self.sx = self.sy = self.ax = self.ay = self.az = 0 - self.bz = self.bc = 0 - + self.output_full_block_if_possible() + self.sx = self.sy = self.ax = self.ay = self.az = -1 + self.bz = self.bc = -1 self.state = 'IDLE' else: # self.putx([0, ['Ignoring: %s (data=%s)' % (cmd, databyte)]])