X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fmaple_bus%2Fpd.py;h=e0dcca736f95f155c6265267a230d3b80cfd52b2;hb=HEAD;hp=861b3f864dcdae9669d83124a7fcaea3705d0d36;hpb=e0e7be8a2f9370032573bcb3b4e7f88b36a2ae2d;p=libsigrokdecode.git

diff --git a/decoders/maple_bus/pd.py b/decoders/maple_bus/pd.py
index 861b3f8..e0dcca7 100644
--- a/decoders/maple_bus/pd.py
+++ b/decoders/maple_bus/pd.py
@@ -18,6 +18,9 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'SDCKA SDCKB')
 
 ann = [
     ['Size', 'L'],
@@ -36,7 +39,8 @@ class Decoder(srd.Decoder):
     desc = 'Maple bus peripheral protocol for SEGA Dreamcast.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['maple_bus']
+    outputs = []
+    tags = ['Retro computing']
     channels = (
         {'id': 'sdcka', 'name': 'SDCKA', 'desc': 'Data/clock line A'},
         {'id': 'sdckb', 'name': 'SDCKB', 'desc': 'Data/clock line B'},
@@ -73,6 +77,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         pass
 
     def start(self):
@@ -138,11 +145,11 @@ class Decoder(srd.Decoder):
         self.putx([7, ['Frame error', 'F error', 'FE']])
 
     def handle_start(self):
-        self.wait({0: 'l', 1: 'h'})
+        self.wait({Pin.SDCKA: 'l', Pin.SDCKB: 'h'})
         self.ss = self.samplenum
         count = 0
         while True:
-            sdcka, sdckb = self.wait([{1: 'f'}, {0: 'r'}])
+            sdcka, sdckb = self.wait([{Pin.SDCKB: 'f'}, {Pin.SDCKA: 'r'}])
             if self.matched[0]:
                 count = count + 1
             if self.matched[1]:
@@ -171,14 +178,15 @@ class Decoder(srd.Decoder):
         countb = 0
         self.data = 0
         while countb < 4:
-            sdcka, sdckb = self.wait([{0: 'f'}, {1: 'f'}])
+            sdcka, sdckb = self.wait([{Pin.SDCKA: 'f'}, {Pin.SDCKB: 'f'}])
             self.es = self.samplenum
             if self.matched[0]:
                 if counta == countb:
                     self.got_bit(sdckb)
                     counta = counta + 1
                 elif counta == 1 and countb == 0 and self.data == 0 and sdckb == 0:
-                    self.wait([{0: 'h', 1: 'h'}, {0: 'f'}, {1: 'f'}])
+                    self.wait([{Pin.SDCKA: 'h', Pin.SDCKB: 'h'},
+                               {Pin.SDCKA: 'f'}, {Pin.SDCKB: 'f'}])
                     self.es = self.samplenum
                     if self.matched[0]:
                         self.got_end()
@@ -198,7 +206,7 @@ class Decoder(srd.Decoder):
                 else:
                     self.frame_error()
                     return False
-        self.wait({0: 'h'})
+        self.wait({Pin.SDCKA: 'h'})
         self.es = self.samplenum
         self.got_byte()
         return True