X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Favr_pdi%2Fpd.py;h=0b3008f9a01ab13c37a63e8721dd1af5551ea0d8;hb=e144452bcdd5f2abbe6b6f3da41ad64f67e39def;hp=1568fdf4b336a5bf5bd95ef35a94e4614fb1f51f;hpb=f0349f7f5bae7cff479772fa9791d3f7f311dfc3;p=libsigrokdecode.git

diff --git a/decoders/avr_pdi/pd.py b/decoders/avr_pdi/pd.py
index 1568fdf..0b3008f 100644
--- a/decoders/avr_pdi/pd.py
+++ b/decoders/avr_pdi/pd.py
@@ -112,14 +112,15 @@ class PDI:
     }
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'avr_pdi'
     name = 'AVR PDI'
     longname = 'Atmel Program and Debug Interface'
-    desc = 'Atmel proprietary interface for the ATxmega MCU.'
+    desc = 'Atmel ATxmega Program and Debug Interface (PDI) protocol.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['pdi']
+    outputs = []
+    tags = ['Debug/trace']
     channels = (
         {'id': 'reset', 'name': 'RESET', 'desc': 'RESET / PDI_CLK'},
         {'id': 'data', 'name': 'DATA', 'desc': 'PDI_DATA'},
@@ -147,17 +148,17 @@ class Decoder(srd.Decoder):
             Ann.PARITY_ERR, Ann.STOP_OK, Ann.STOP_ERR, Ann.BREAK)),
         ('pdi_fields', 'PDI fields', (Ann.OPCODE, Ann.DATA_PROG, Ann.DATA_DEV,
             Ann.PDI_BREAK)),
-        ('pdi_cmds', 'PDI Cmds', (Ann.ENABLE, Ann.DISABLE, Ann.COMMAND)),
+        ('pdi_cmds', 'PDI commands', (Ann.ENABLE, Ann.DISABLE, Ann.COMMAND)),
     )
     binary = (
         ('bytes', 'PDI protocol bytes'),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
-        # Detect input changes and clock edges.
-        self.prev_pins = None
-        self.prev_clock = None
         self.clear_state()
 
     def clear_state(self):
@@ -546,12 +547,7 @@ class Decoder(srd.Decoder):
         # Reset internal state for the next frame.
         self.bits = []
 
-    def find_clk_edge(self, samplenum, clock_pin, data_pin):
-        # Ignore the sample if the clock pin has not changed.
-        if clock_pin == self.prev_clock:
-            return
-        self.prev_clock = clock_pin
-
+    def handle_clk_edge(self, clock_pin, data_pin):
         # Sample the data line on rising clock edges. Always, for TX and for
         # RX bytes alike.
         if clock_pin == 1:
@@ -564,7 +560,7 @@ class Decoder(srd.Decoder):
         # periods (avoid interpreting the DATA line when the "enabled" state
         # has not yet been determined).
         self.ss_last_fall = self.ss_curr_fall
-        self.ss_curr_fall = samplenum
+        self.ss_curr_fall = self.samplenum
         if self.ss_last_fall is None:
             return
 
@@ -573,14 +569,6 @@ class Decoder(srd.Decoder):
         bit_val = self.data_sample
         self.handle_bits(bit_ss, bit_es, bit_val)
 
-    def decode(self, ss, es, data):
-        for samplenum, pins in data:
-
-            # Ignore identical samples.
-            if self.prev_pins == pins:
-                continue
-            self.prev_pins = pins
-
-            # Have DATA processed at appropriate clock edges.
-            clock_pin, data_pin = pins[0], pins[1]
-            self.find_clk_edge(samplenum, clock_pin, data_pin)
+    def decode(self):
+        while True:
+            self.handle_clk_edge(*self.wait({0: 'e'}))