X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;ds=inline;f=decoders%2Fuart%2Fpd.py;h=1639727c3c8cf2983158a03bee1c648ceebd074d;hb=2aa30631c0e0d54f3e71c88107ae153b8a1c5426;hp=fa1bca9d3ece8f662fdc1a62f44c9a3f30200630;hpb=4c180223a8ae12feb7bc3601e07e848fb9cdb493;p=libsigrokdecode.git

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index fa1bca9..1639727 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -87,7 +87,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
-    tags = ['Logic', 'Bus']
+    tags = ['Embedded/industrial']
     optional_channels = (
         # Allow specifying only one of the signals, e.g. if only one data
         # direction exists (or is relevant).
@@ -112,6 +112,12 @@ class Decoder(srd.Decoder):
             'values': ('yes', 'no')},
         {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no',
             'values': ('yes', 'no')},
+        {'id': 'rx_packet_delimiter', 'desc': 'RX packet delimiter (decimal)',
+            'default': -1},
+        {'id': 'tx_packet_delimiter', 'desc': 'TX packet delimiter (decimal)',
+            'default': -1},
+        {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
+        {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
     )
     annotations = (
         ('rx-data', 'RX data'),
@@ -130,16 +136,20 @@ class Decoder(srd.Decoder):
         ('tx-data-bits', 'TX data bits'),
         ('rx-break', 'RX break'),
         ('tx-break', 'TX break'),
+        ('rx-packet', 'RX packet'),
+        ('tx-packet', 'TX packet'),
     )
     annotation_rows = (
         ('rx-data', 'RX', (0, 2, 4, 6, 8)),
         ('rx-data-bits', 'RX bits', (12,)),
         ('rx-warnings', 'RX warnings', (10,)),
         ('rx-break', 'RX break', (14,)),
+        ('rx-packets', 'RX packets', (16,)),
         ('tx-data', 'TX', (1, 3, 5, 7, 9)),
         ('tx-data-bits', 'TX bits', (13,)),
         ('tx-warnings', 'TX warnings', (11,)),
         ('tx-break', 'TX break', (15,)),
+        ('tx-packets', 'TX packets', (17,)),
     )
     binary = (
         ('rx', 'RX dump'),
@@ -152,6 +162,10 @@ class Decoder(srd.Decoder):
         s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
         self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
 
+    def putx_packet(self, rxtx, data):
+        s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0
+        self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
+
     def putpx(self, rxtx, data):
         s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
         self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
@@ -191,6 +205,8 @@ class Decoder(srd.Decoder):
         self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
         self.databits = [[], []]
         self.break_start = [None, None]
+        self.packet_cache = [[], []]
+        self.ss_packet, self.es_packet = [None, None], [None, None]
 
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
@@ -246,6 +262,30 @@ class Decoder(srd.Decoder):
 
         self.state[rxtx] = 'GET DATA BITS'
 
+    def handle_packet(self, rxtx):
+        d = 'rx' if (rxtx == RX) else 'tx'
+        delim = self.options[d + '_packet_delimiter']
+        plen = self.options[d + '_packet_len']
+        if delim == -1 and plen == -1:
+            return
+
+        # Cache data values until we see the delimiter and/or the specified
+        # packet length has been reached (whichever happens first).
+        if len(self.packet_cache[rxtx]) == 0:
+            self.ss_packet[rxtx] = self.startsample[rxtx]
+        self.packet_cache[rxtx].append(self.datavalue[rxtx])
+        if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
+            self.es_packet[rxtx] = self.samplenum
+            s = ''
+            for b in self.packet_cache[rxtx]:
+                s += self.format_value(b)
+                if self.options['format'] != 'ascii':
+                    s += ' '
+            if self.options['format'] != 'ascii' and s[-1] == ' ':
+                s = s[:-1] # Drop trailing space.
+            self.putx_packet(rxtx, [16 + rxtx, [s]])
+            self.packet_cache[rxtx] = []
+
     def get_data_bits(self, rxtx, signal):
         # Save the sample number of the middle of the first data bit.
         if self.startsample[rxtx] == -1:
@@ -279,6 +319,8 @@ class Decoder(srd.Decoder):
         self.putbin(rxtx, [rxtx, bdata])
         self.putbin(rxtx, [2, bdata])
 
+        self.handle_packet(rxtx)
+
         self.databits[rxtx] = []
 
         # Advance to either reception of the parity bit, or reception of