From: Gerhard Sittig <redacted>
Date: Sun, 18 Jun 2017 18:02:46 +0000 (+0200)
Subject: ir_rc5: Rephrase open coded value for start bit 1
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=fcbd63364b64383c437c6182110557ac30201a1f;p=libsigrokdecode.git

ir_rc5: Rephrase open coded value for start bit 1

Make obvious that the start bit's value is 1 in the IDLE stage.
---

diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py
index ae29f10..edb29bd 100644
--- a/decoders/ir_rc5/pd.py
+++ b/decoders/ir_rc5/pd.py
@@ -147,8 +147,9 @@ class Decoder(srd.Decoder):
 
             # State machine.
             if self.state == 'IDLE':
+                bit = 1
                 self.edges.append(self.samplenum)
-                self.bits.append([self.samplenum, 1])
+                self.bits.append([self.samplenum, bit])
                 self.state = 'MID1'
                 self.old_ir = self.ir
                 continue