From: Uwe Hermann <redacted>
Date: Thu, 10 Aug 2017 22:36:44 +0000 (+0200)
Subject: Add a square wave digital + analog capture.
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=f711de81a725d61c027b45d2fd51efaecb17b4e4;p=sigrok-dumps.git

Add a square wave digital + analog capture.
---

diff --git a/misc/square_wave_analog/100khz_clock_2logic_1analog.sr b/misc/square_wave_analog/100khz_clock_2logic_1analog.sr
new file mode 100644
index 0000000..670e8bc
Binary files /dev/null and b/misc/square_wave_analog/100khz_clock_2logic_1analog.sr differ
diff --git a/misc/square_wave_analog/README b/misc/square_wave_analog/README
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index 0000000..267d41e
--- /dev/null
+++ b/misc/square_wave_analog/README
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+Analog clock signal
+-------------------------------------------------------------------------------
+
+This is a set of example captures of a clock signal (rectangle signal)
+generated using a function generator, sampled using an LA/MSO.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a Noname LHT00SU1 (at 12MHz):
+
+  Probe       Signal
+  -------------------------------
+  1DCH        100kHz clock signal
+  2DCH        same 100kHz clock signal
+  1ACH        same 100kHz clock signal
+