From: Gerhard Sittig <redacted>
Date: Fri, 17 Jul 2020 07:17:02 +0000 (+0200)
Subject: pjdl: support PAD bit adjacent to last HIGH DATA bit (no LOW)
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=f138ba194e11d517d7b2c8a4a7861f71a8773128;p=libsigrokdecode.git

pjdl: support PAD bit adjacent to last HIGH DATA bit (no LOW)

The PJDL decoder's previous implementation was incomplete. It assumed
that PAD bits always start with a rising edge. Which made the decoder
miss the next byte when a previous byte's MSB is set, and the last DATA
bit and the next PAD bit kept the signal HIGH between them (no LOW phase
was seen between these symbols).

Keep the check for the LOW level after the byte's last DATA bit within
the bit times' tolerance. But accept when the level remains HIGH, and
check for the HIGH bit's width starting from the end of the last DATA
bit. Also start the PAD bit's annotation from that "virtual" edge.

This patch is based on a fix that was
Submitted-By: Julio Aguirre <redacted>
---

diff --git a/decoders/pjdl/pd.py b/decoders/pjdl/pd.py
index dc30358..d5cc39f 100644
--- a/decoders/pjdl/pd.py
+++ b/decoders/pjdl/pd.py
@@ -510,7 +510,9 @@ class Decoder(srd.Decoder):
             is_short = bit_level and self.span_is_short(span)
 
             if is_pad:
-                ss, es = last_snum, curr_snum
+                # BEWARE! Use ss value of last edge (genuinely seen, or
+                # inserted after a DATA byte) for PAD bit annotations.
+                ss, es = self.edges[-2], curr_snum
                 texts = ['PAD', '{:d}'.format(bit_level)]
                 self.putg(ss, es, [ANN_PAD_BIT, texts])
                 self.symbols_append(ss, es, 'PAD_BIT', bit_level)
@@ -674,10 +676,20 @@ class Decoder(srd.Decoder):
             # the transmitter's and the sender's timings differ within a
             # margin, and the transmitter may hold the last DATA bit's
             # HIGH level for a little longer.
+            #
+            # When no falling edge is seen within the maximum tolerance
+            # for the last DATA bit, then this could be the combination
+            # of a HIGH DATA bit and a PAD bit without a LOW in between.
+            # Fake an edge in that case, to re-use existing code paths.
+            # Make sure to keep referencing times to the last SYNC pad's
+            # falling edge. This is the last reliable condition we have.
             if curr_level:
                 hold = self.hold_high_width
                 curr_level, = self.wait([{PIN_DATA: 'l'}, {'skip': int(hold)}])
                 self.carrier_check(curr_level, self.samplenum)
+                if self.matched[1]:
+                    self.edges.append(curr_snum)
+                    curr_level = 1 - curr_level
                 curr_snum = self.samplenum
 
             # Get the byte value from the bits (when available).