From: Gerhard Sittig <redacted>
Date: Sat, 7 Nov 2020 13:47:21 +0000 (+0100)
Subject: parallel: add option to sample data on either clock edge
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=e2317ec49b8b04c7f8b3358c2e9c264de4280539;p=libsigrokdecode.git

parallel: add option to sample data on either clock edge

Add 'either' as another choice in addition to rising and falling clock
edge. This is useful since parallel busses exist which communicate at
double data rate (DDR).

Unobfuscate the mapping between displayed option text and .wait()
condition codes while we are here.
---

diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index 10255f3..abf48eb 100644
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -86,7 +86,7 @@ class Decoder(srd.Decoder):
     )
     options = (
         {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
-            'default': 'rising', 'values': ('rising', 'falling')},
+            'default': 'rising', 'values': ('rising', 'falling', 'either')},
         {'id': 'wordsize', 'desc': 'Data wordsize (# bus cycles)',
             'default': 0},
         {'id': 'endianness', 'desc': 'Data endianness',
@@ -204,7 +204,11 @@ class Decoder(srd.Decoder):
         # which provide input data.
         has_clock = self.has_channel(Pin.CLOCK)
         if has_clock:
-            edge = self.options['clock_edge'][0]
+            edge = {
+                'rising': 'r',
+                'falling': 'f',
+                'either': 'e',
+            }.get(self.options['clock_edge'])
             conds = [{Pin.CLOCK: edge}]
         else:
             conds = [{idx: 'e'} for idx in has_data]