From: Uwe Hermann Date: Sat, 15 Apr 2017 18:17:24 +0000 (+0200) Subject: scopes: Factor out CTL_BIT, OUT0, and OE_CTL. X-Git-Tag: sigrok-firmware-fx2lafw-0.1.6~20 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=e1c5ba21853765725d723efdef22bedef7cfecc6;p=sigrok-firmware-fx2lafw.git scopes: Factor out CTL_BIT, OUT0, and OE_CTL. --- diff --git a/hantek_6022be.c b/hantek_6022be.c index 67d77e85..93665b8d 100644 --- a/hantek_6022be.c +++ b/hantek_6022be.c @@ -33,6 +33,12 @@ #define LED_GREEN() PC0 = 1; PC1 = 0; #define LED_RED() PC0 = 0; PC1 = 1; +/* CTLx pin index (IFCLK, ADC clock input). */ +#define CTL_BIT 2 + +#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */ +#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */ + /* Change to support as many interfaces as you need. */ static BYTE altiface = 0; @@ -224,16 +230,16 @@ static const struct samplerate_info { } samplerates[] = { { 48, 0x80, 0, 3, 0, 0x00, 0xea }, { 30, 0x80, 0, 3, 0, 0x00, 0xaa }, - { 24, 1, 0, 2, 1, 0x40, 0xca }, - { 16, 1, 1, 2, 0, 0x40, 0xca }, - { 12, 2, 1, 2, 0, 0x40, 0xca }, - { 8, 3, 2, 2, 0, 0x40, 0xca }, - { 4, 6, 5, 2, 0, 0x40, 0xca }, - { 2, 12, 11, 2, 0, 0x40, 0xca }, - { 1, 24, 23, 2, 0, 0x40, 0xca }, - { 50, 48, 47, 2, 0, 0x40, 0xca }, - { 20, 120, 119, 2, 0, 0x40, 0xca }, - { 10, 240, 239, 2, 0, 0x40, 0xca }, + { 24, 1, 0, 2, 1, OUT0, 0xca }, + { 16, 1, 1, 2, 0, OUT0, 0xca }, + { 12, 2, 1, 2, 0, OUT0, 0xca }, + { 8, 3, 2, 2, 0, OUT0, 0xca }, + { 4, 6, 5, 2, 0, OUT0, 0xca }, + { 2, 12, 11, 2, 0, OUT0, 0xca }, + { 1, 24, 23, 2, 0, OUT0, 0xca }, + { 50, 48, 47, 2, 0, OUT0, 0xca }, + { 20, 120, 119, 2, 0, OUT0, 0xca }, + { 10, 240, 239, 2, 0, OUT0, 0xca }, }; static BOOL set_samplerate(BYTE rate) @@ -290,8 +296,8 @@ static BOOL set_samplerate(BYTE rate) /* OUTPUT 0-7 */ EXTAUTODAT2 = samplerates[i].out0; - EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */ - EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */ + EXTAUTODAT2 = OE_CTL; + EXTAUTODAT2 = OE_CTL; EXTAUTODAT2 = 0; EXTAUTODAT2 = 0; EXTAUTODAT2 = 0; diff --git a/hantek_6022bl.c b/hantek_6022bl.c index d637c822..66fc1de7 100644 --- a/hantek_6022bl.c +++ b/hantek_6022bl.c @@ -33,6 +33,12 @@ #define LED_GREEN() PC0 = 1; PC1 = 0; #define LED_RED() PC0 = 0; PC1 = 1; +/* CTLx pin index (IFCLK, ADC clock input). */ +#define CTL_BIT 0 + +#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */ +#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */ + /* Change to support as many interfaces as you need. */ static BYTE altiface = 0; @@ -225,16 +231,16 @@ static const struct samplerate_info { } samplerates[] = { { 48, 0x80, 0, 3, 0, 0x00, 0xea }, { 30, 0x80, 0, 3, 0, 0x00, 0xaa }, - { 24, 1, 0, 2, 1, 0x10, 0xca }, - { 16, 1, 1, 2, 0, 0x10, 0xca }, - { 12, 2, 1, 2, 0, 0x10, 0xca }, - { 8, 3, 2, 2, 0, 0x10, 0xca }, - { 4, 6, 5, 2, 0, 0x10, 0xca }, - { 2, 12, 11, 2, 0, 0x10, 0xca }, - { 1, 24, 23, 2, 0, 0x10, 0xca }, - { 50, 48, 47, 2, 0, 0x10, 0xca }, - { 20, 120, 119, 2, 0, 0x10, 0xca }, - { 10, 240, 239, 2, 0, 0x10, 0xca }, + { 24, 1, 0, 2, 1, OUT0, 0xca }, + { 16, 1, 1, 2, 0, OUT0, 0xca }, + { 12, 2, 1, 2, 0, OUT0, 0xca }, + { 8, 3, 2, 2, 0, OUT0, 0xca }, + { 4, 6, 5, 2, 0, OUT0, 0xca }, + { 2, 12, 11, 2, 0, OUT0, 0xca }, + { 1, 24, 23, 2, 0, OUT0, 0xca }, + { 50, 48, 47, 2, 0, OUT0, 0xca }, + { 20, 120, 119, 2, 0, OUT0, 0xca }, + { 10, 240, 239, 2, 0, OUT0, 0xca }, }; static BOOL set_samplerate(BYTE rate) @@ -291,8 +297,8 @@ static BOOL set_samplerate(BYTE rate) /* OUTPUT 0-7 */ EXTAUTODAT2 = samplerates[i].out0; - EXTAUTODAT2 = 0x11; /* OE0=1, CTL0=1 */ - EXTAUTODAT2 = 0x11; /* OE0=1, CTL0=1 */ + EXTAUTODAT2 = OE_CTL; + EXTAUTODAT2 = OE_CTL; EXTAUTODAT2 = 0; EXTAUTODAT2 = 0; EXTAUTODAT2 = 0; diff --git a/sainsmart_dds120.c b/sainsmart_dds120.c index 8a05df19..e4ba51c4 100644 --- a/sainsmart_dds120.c +++ b/sainsmart_dds120.c @@ -34,6 +34,12 @@ #define LED_GREEN() NOP #define LED_RED() NOP +/* CTLx pin index (IFCLK, ADC clock input). */ +#define CTL_BIT 2 + +#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */ +#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */ + /* Change to support as many interfaces as you need. */ static BYTE altiface = 0; @@ -280,21 +286,21 @@ static const struct samplerate_info { } samplerates[] = { { 48, 0x80, 0, 3, 0, 0x00, 0xea }, { 30, 0x80, 0, 3, 0, 0x00, 0xaa }, - { 24, 1, 0, 2, 1, 0x40, 0xea }, - { 16, 1, 1, 2, 0, 0x40, 0xea }, - { 15, 1, 0, 2, 1, 0x40, 0xaa }, - { 12, 2, 1, 2, 0, 0x40, 0xea }, - { 11, 1, 1, 2, 0, 0x40, 0xaa }, - { 8, 3, 2, 2, 0, 0x40, 0xea }, - { 6, 2, 2, 2, 0, 0x40, 0xaa }, - { 5, 3, 2, 2, 0, 0x40, 0xaa }, - { 4, 6, 5, 2, 0, 0x40, 0xea }, - { 3, 5, 4, 2, 0, 0x40, 0xaa }, - { 2, 12, 11, 2, 0, 0x40, 0xea }, - { 1, 24, 23, 2, 0, 0x40, 0xea }, - { 50, 48, 47, 2, 0, 0x40, 0xea }, - { 20, 120, 119, 2, 0, 0x40, 0xea }, - { 10, 240, 239, 2, 0, 0x40, 0xea }, + { 24, 1, 0, 2, 1, OUT0, 0xea }, + { 16, 1, 1, 2, 0, OUT0, 0xea }, + { 15, 1, 0, 2, 1, OUT0, 0xaa }, + { 12, 2, 1, 2, 0, OUT0, 0xea }, + { 11, 1, 1, 2, 0, OUT0, 0xaa }, + { 8, 3, 2, 2, 0, OUT0, 0xea }, + { 6, 2, 2, 2, 0, OUT0, 0xaa }, + { 5, 3, 2, 2, 0, OUT0, 0xaa }, + { 4, 6, 5, 2, 0, OUT0, 0xea }, + { 3, 5, 4, 2, 0, OUT0, 0xaa }, + { 2, 12, 11, 2, 0, OUT0, 0xea }, + { 1, 24, 23, 2, 0, OUT0, 0xea }, + { 50, 48, 47, 2, 0, OUT0, 0xea }, + { 20, 120, 119, 2, 0, OUT0, 0xea }, + { 10, 240, 239, 2, 0, OUT0, 0xea }, }; static BOOL set_samplerate(BYTE rate) @@ -351,8 +357,8 @@ static BOOL set_samplerate(BYTE rate) /* OUTPUT 0-7 */ EXTAUTODAT2 = samplerates[i].out0; - EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */ - EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */ + EXTAUTODAT2 = OE_CTL; + EXTAUTODAT2 = OE_CTL; EXTAUTODAT2 = 0; EXTAUTODAT2 = 0; EXTAUTODAT2 = 0;